JS
John Swenson
Mon, Jun 13, 2016 3:50 AM
Hi TimeNuts, this is my first post to this list, I've been reading it
for years but haven't needed to post, now I'm starting a project and
need some advice.
I need to do a bunch of phase noise measurements but can't afford the
"big guys", the TimePod seems perfect and since the schematic has been
published I decided I would try my hand at making my own version.
I'm just doing phase noise measurements of digital clocks (square waves)
so it seems to me I don't need some of the circuitry in the TimePod, in
particular the digitally controlled RF attenuators and the ADCs
themselves. My idea is to use LVPECL flip-flops to sample the DUT and
reference clocks, convert the differential outputs to CMOS and feed the
FPGA inputs from that. Yes you loose AM noise riding on top of the
square wave, but is that really necessary for just square wave phase
noise measurements?
For a first pass cheap and dirty version of this I was planning on using
the LVPECL version of the Crystek 575 for the sample clock, will this
work? The TimePod schematic shows a VTUNE signal fed to the OCXO, if I
don't use that is something going to break? In other words will timelab
try and tweak the sample freaquency and get confused when nothing happens?
I plan on using the 2 reference clock measurement technique, but have a
couple questions about this. In the TimePod ch 0 and 2 are the input,
with separate jacks available. The "ref" input goes to ch 1 and 3. So it
looks like the two references have to go to 0 and 2 and the DUT to 1 and
3, even though that puts the references on the "input" and the DUT on
the "reference". Do you need to do anything special in TimeLab to
support this or does it automatically support it? Since I am doing my
own hardware and have four independent inputs do I do the same thing
(ref clocks on 0 and 2 and DUT on 1 and 3) or put the refs on 1 and 3
and the DUT on 0 and 2?
Any thoughts?
Thanks,
John S.
Hi TimeNuts, this is my first post to this list, I've been reading it
for years but haven't needed to post, now I'm starting a project and
need some advice.
I need to do a bunch of phase noise measurements but can't afford the
"big guys", the TimePod seems perfect and since the schematic has been
published I decided I would try my hand at making my own version.
I'm just doing phase noise measurements of digital clocks (square waves)
so it seems to me I don't need some of the circuitry in the TimePod, in
particular the digitally controlled RF attenuators and the ADCs
themselves. My idea is to use LVPECL flip-flops to sample the DUT and
reference clocks, convert the differential outputs to CMOS and feed the
FPGA inputs from that. Yes you loose AM noise riding on top of the
square wave, but is that really necessary for just square wave phase
noise measurements?
For a first pass cheap and dirty version of this I was planning on using
the LVPECL version of the Crystek 575 for the sample clock, will this
work? The TimePod schematic shows a VTUNE signal fed to the OCXO, if I
don't use that is something going to break? In other words will timelab
try and tweak the sample freaquency and get confused when nothing happens?
I plan on using the 2 reference clock measurement technique, but have a
couple questions about this. In the TimePod ch 0 and 2 are the input,
with separate jacks available. The "ref" input goes to ch 1 and 3. So it
looks like the two references have to go to 0 and 2 and the DUT to 1 and
3, even though that puts the references on the "input" and the DUT on
the "reference". Do you need to do anything special in TimeLab to
support this or does it automatically support it? Since I am doing my
own hardware and have four independent inputs do I do the same thing
(ref clocks on 0 and 2 and DUT on 1 and 3) or put the refs on 1 and 3
and the DUT on 0 and 2?
Any thoughts?
Thanks,
John S.
BG
Bruce Griffiths
Mon, Jun 13, 2016 7:51 AM
Adjusting the sampling clock frequency so that is neither a harmonic nor a harmonic of a subharmonic of either of the clock frequencies being compared ensures that each clock waveform isnt repeatedly sampled at a small set of points.i.e.
fsample != (m/n)*ftest
andfsample != (p/q)*freference
where m,n,p,q are integers.
When using a dual reference the difference between the frequencies of the pair of reference sources should be significantly less than the lowest offset frequency of interest.
Bruce
On Monday, 13 June 2016 6:00 PM, John Swenson <johnswenson1@comcast.net> wrote:
Hi TimeNuts, this is my first post to this list, I've been reading it
for years but haven't needed to post, now I'm starting a project and
need some advice.
I need to do a bunch of phase noise measurements but can't afford the
"big guys", the TimePod seems perfect and since the schematic has been
published I decided I would try my hand at making my own version.
I'm just doing phase noise measurements of digital clocks (square waves)
so it seems to me I don't need some of the circuitry in the TimePod, in
particular the digitally controlled RF attenuators and the ADCs
themselves. My idea is to use LVPECL flip-flops to sample the DUT and
reference clocks, convert the differential outputs to CMOS and feed the
FPGA inputs from that. Yes you loose AM noise riding on top of the
square wave, but is that really necessary for just square wave phase
noise measurements?
For a first pass cheap and dirty version of this I was planning on using
the LVPECL version of the Crystek 575 for the sample clock, will this
work? The TimePod schematic shows a VTUNE signal fed to the OCXO, if I
don't use that is something going to break? In other words will timelab
try and tweak the sample freaquency and get confused when nothing happens?
I plan on using the 2 reference clock measurement technique, but have a
couple questions about this. In the TimePod ch 0 and 2 are the input,
with separate jacks available. The "ref" input goes to ch 1 and 3. So it
looks like the two references have to go to 0 and 2 and the DUT to 1 and
3, even though that puts the references on the "input" and the DUT on
the "reference". Do you need to do anything special in TimeLab to
support this or does it automatically support it? Since I am doing my
own hardware and have four independent inputs do I do the same thing
(ref clocks on 0 and 2 and DUT on 1 and 3) or put the refs on 1 and 3
and the DUT on 0 and 2?
Any thoughts?
Thanks,
John S.
time-nuts mailing list -- time-nuts@febo.com
To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts
and follow the instructions there.
Adjusting the sampling clock frequency so that is neither a harmonic nor a harmonic of a subharmonic of either of the clock frequencies being compared ensures that each clock waveform isnt repeatedly sampled at a small set of points.i.e.
fsample != (m/n)*ftest
andfsample != (p/q)*freference
where m,n,p,q are integers.
When using a dual reference the difference between the frequencies of the pair of reference sources should be significantly less than the lowest offset frequency of interest.
Bruce
On Monday, 13 June 2016 6:00 PM, John Swenson <johnswenson1@comcast.net> wrote:
Hi TimeNuts, this is my first post to this list, I've been reading it
for years but haven't needed to post, now I'm starting a project and
need some advice.
I need to do a bunch of phase noise measurements but can't afford the
"big guys", the TimePod seems perfect and since the schematic has been
published I decided I would try my hand at making my own version.
I'm just doing phase noise measurements of digital clocks (square waves)
so it seems to me I don't need some of the circuitry in the TimePod, in
particular the digitally controlled RF attenuators and the ADCs
themselves. My idea is to use LVPECL flip-flops to sample the DUT and
reference clocks, convert the differential outputs to CMOS and feed the
FPGA inputs from that. Yes you loose AM noise riding on top of the
square wave, but is that really necessary for just square wave phase
noise measurements?
For a first pass cheap and dirty version of this I was planning on using
the LVPECL version of the Crystek 575 for the sample clock, will this
work? The TimePod schematic shows a VTUNE signal fed to the OCXO, if I
don't use that is something going to break? In other words will timelab
try and tweak the sample freaquency and get confused when nothing happens?
I plan on using the 2 reference clock measurement technique, but have a
couple questions about this. In the TimePod ch 0 and 2 are the input,
with separate jacks available. The "ref" input goes to ch 1 and 3. So it
looks like the two references have to go to 0 and 2 and the DUT to 1 and
3, even though that puts the references on the "input" and the DUT on
the "reference". Do you need to do anything special in TimeLab to
support this or does it automatically support it? Since I am doing my
own hardware and have four independent inputs do I do the same thing
(ref clocks on 0 and 2 and DUT on 1 and 3) or put the refs on 1 and 3
and the DUT on 0 and 2?
Any thoughts?
Thanks,
John S.
_______________________________________________
time-nuts mailing list -- time-nuts@febo.com
To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts
and follow the instructions there.
BC
Bob Camp
Mon, Jun 13, 2016 11:42 AM
Hi
What sort of phase noise levels are you trying to measure? If you are after -80 dbc/Hz sort of numbers, there are a lot of ways
to do the job. For low noise stuff (-160 dbc/ Hz) the quickest way to do it is a mixer / two oscillators in quadrature and a sound
card. The “pure digital” equivalent of that is an XOR gate running into a sound card. The XOR is not as quiet as a proper mixer.
The “detector” (ADC / mixer / XOR) is what sets the noise floor and limits measurement capabilities of the device.
Bob
On Jun 12, 2016, at 11:50 PM, John Swenson johnswenson1@comcast.net wrote:
Hi TimeNuts, this is my first post to this list, I've been reading it for years but haven't needed to post, now I'm starting a project and need some advice.
I need to do a bunch of phase noise measurements but can't afford the "big guys", the TimePod seems perfect and since the schematic has been published I decided I would try my hand at making my own version.
I'm just doing phase noise measurements of digital clocks (square waves) so it seems to me I don't need some of the circuitry in the TimePod, in particular the digitally controlled RF attenuators and the ADCs themselves. My idea is to use LVPECL flip-flops to sample the DUT and reference clocks, convert the differential outputs to CMOS and feed the FPGA inputs from that. Yes you loose AM noise riding on top of the square wave, but is that really necessary for just square wave phase noise measurements?
For a first pass cheap and dirty version of this I was planning on using the LVPECL version of the Crystek 575 for the sample clock, will this work? The TimePod schematic shows a VTUNE signal fed to the OCXO, if I don't use that is something going to break? In other words will timelab try and tweak the sample freaquency and get confused when nothing happens?
I plan on using the 2 reference clock measurement technique, but have a couple questions about this. In the TimePod ch 0 and 2 are the input, with separate jacks available. The "ref" input goes to ch 1 and 3. So it looks like the two references have to go to 0 and 2 and the DUT to 1 and 3, even though that puts the references on the "input" and the DUT on the "reference". Do you need to do anything special in TimeLab to support this or does it automatically support it? Since I am doing my own hardware and have four independent inputs do I do the same thing (ref clocks on 0 and 2 and DUT on 1 and 3) or put the refs on 1 and 3 and the DUT on 0 and 2?
Any thoughts?
Thanks,
John S.
time-nuts mailing list -- time-nuts@febo.com
To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts
and follow the instructions there.
Hi
What sort of phase noise levels are you trying to measure? If you are after -80 dbc/Hz sort of numbers, there are a lot of ways
to do the job. For low noise stuff (-160 dbc/ Hz) the quickest way to do it is a mixer / two oscillators in quadrature and a sound
card. The “pure digital” equivalent of that is an XOR gate running into a sound card. The XOR is not as quiet as a proper mixer.
The “detector” (ADC / mixer / XOR) is what sets the noise floor and limits measurement capabilities of the device.
Bob
> On Jun 12, 2016, at 11:50 PM, John Swenson <johnswenson1@comcast.net> wrote:
>
> Hi TimeNuts, this is my first post to this list, I've been reading it for years but haven't needed to post, now I'm starting a project and need some advice.
>
> I need to do a bunch of phase noise measurements but can't afford the "big guys", the TimePod seems perfect and since the schematic has been published I decided I would try my hand at making my own version.
>
> I'm just doing phase noise measurements of digital clocks (square waves) so it seems to me I don't need some of the circuitry in the TimePod, in particular the digitally controlled RF attenuators and the ADCs themselves. My idea is to use LVPECL flip-flops to sample the DUT and reference clocks, convert the differential outputs to CMOS and feed the FPGA inputs from that. Yes you loose AM noise riding on top of the square wave, but is that really necessary for just square wave phase noise measurements?
>
> For a first pass cheap and dirty version of this I was planning on using the LVPECL version of the Crystek 575 for the sample clock, will this work? The TimePod schematic shows a VTUNE signal fed to the OCXO, if I don't use that is something going to break? In other words will timelab try and tweak the sample freaquency and get confused when nothing happens?
>
> I plan on using the 2 reference clock measurement technique, but have a couple questions about this. In the TimePod ch 0 and 2 are the input, with separate jacks available. The "ref" input goes to ch 1 and 3. So it looks like the two references have to go to 0 and 2 and the DUT to 1 and 3, even though that puts the references on the "input" and the DUT on the "reference". Do you need to do anything special in TimeLab to support this or does it automatically support it? Since I am doing my own hardware and have four independent inputs do I do the same thing (ref clocks on 0 and 2 and DUT on 1 and 3) or put the refs on 1 and 3 and the DUT on 0 and 2?
>
> Any thoughts?
>
> Thanks,
>
> John S.
> _______________________________________________
> time-nuts mailing list -- time-nuts@febo.com
> To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts
> and follow the instructions there.
CC
Chris Caudle
Mon, Jun 13, 2016 1:28 PM
On Sun, June 12, 2016 10:50 pm, John Swenson wrote:
I'm just doing phase noise measurements of digital clocks (square waves)
so it seems to me I don't need some of the circuitry in the TimePod, in
particular the digitally controlled RF attenuators and the ADCs
themselves. My idea is to use LVPECL flip-flops to sample the DUT and
reference clocks, convert the differential outputs to CMOS and feed the
FPGA inputs from that. Yes you loose AM noise riding on top of the
square wave, but is that really necessary for just square wave phase
noise measurements?
Are the FPGA inputs low enough noise for that? With an ADC the time
resolution is a combination of clock noise and input noise, for most high
quality ADC the effective time resolution you can achieve by analyzing the
output data stream is much higher than the resolution of the clock period.
Can you achieve similar with just a single bit quantizer based on the FPGA
CMOS inputs?
--
Chris Caudle
On Sun, June 12, 2016 10:50 pm, John Swenson wrote:
> I'm just doing phase noise measurements of digital clocks (square waves)
> so it seems to me I don't need some of the circuitry in the TimePod, in
> particular the digitally controlled RF attenuators and the ADCs
> themselves. My idea is to use LVPECL flip-flops to sample the DUT and
> reference clocks, convert the differential outputs to CMOS and feed the
> FPGA inputs from that. Yes you loose AM noise riding on top of the
> square wave, but is that really necessary for just square wave phase
> noise measurements?
Are the FPGA inputs low enough noise for that? With an ADC the time
resolution is a combination of clock noise and input noise, for most high
quality ADC the effective time resolution you can achieve by analyzing the
output data stream is much higher than the resolution of the clock period.
Can you achieve similar with just a single bit quantizer based on the FPGA
CMOS inputs?
--
Chris Caudle
JS
John Swenson
Mon, Jun 13, 2016 4:54 PM
The sampling will be done by a set of ECL flops. The FPGA is reading the
already sampled ECL outputs. (with ECL to CMOS converters) I'm using a
hex ECL register with one clock input for all six flops,
The ECL input circuit is a differential amplifier, I will be feeding the
CMOS level input to one side and the other side will be a very low noise
reference voltage set to half the CMOS voltage (1.65V for 3.3V square
wave).
I really don't know the input noise of that differential amp, but it is
probably much better than a normal CMOS input. I guess I will find out!
The particular chip says it has a max of 100fs additive jitter on the
output from the input clock. But that is output jitter, I don't really
care about output jitter, it is sampling jitter that is important here,
I'm not sure how those two correlate.
John S.
On 6/13/2016 6:28 AM, Chris Caudle wrote:
On Sun, June 12, 2016 10:50 pm, John Swenson wrote:
I'm just doing phase noise measurements of digital clocks (square waves)
so it seems to me I don't need some of the circuitry in the TimePod, in
particular the digitally controlled RF attenuators and the ADCs
themselves. My idea is to use LVPECL flip-flops to sample the DUT and
reference clocks, convert the differential outputs to CMOS and feed the
FPGA inputs from that. Yes you loose AM noise riding on top of the
square wave, but is that really necessary for just square wave phase
noise measurements?
Are the FPGA inputs low enough noise for that? With an ADC the time
resolution is a combination of clock noise and input noise, for most high
quality ADC the effective time resolution you can achieve by analyzing the
output data stream is much higher than the resolution of the clock period.
Can you achieve similar with just a single bit quantizer based on the FPGA
CMOS inputs?
The sampling will be done by a set of ECL flops. The FPGA is reading the
already sampled ECL outputs. (with ECL to CMOS converters) I'm using a
hex ECL register with one clock input for all six flops,
The ECL input circuit is a differential amplifier, I will be feeding the
CMOS level input to one side and the other side will be a very low noise
reference voltage set to half the CMOS voltage (1.65V for 3.3V square
wave).
I really don't know the input noise of that differential amp, but it is
probably much better than a normal CMOS input. I guess I will find out!
The particular chip says it has a max of 100fs additive jitter on the
output from the input clock. But that is output jitter, I don't really
care about output jitter, it is sampling jitter that is important here,
I'm not sure how those two correlate.
John S.
On 6/13/2016 6:28 AM, Chris Caudle wrote:
> On Sun, June 12, 2016 10:50 pm, John Swenson wrote:
>> I'm just doing phase noise measurements of digital clocks (square waves)
>> so it seems to me I don't need some of the circuitry in the TimePod, in
>> particular the digitally controlled RF attenuators and the ADCs
>> themselves. My idea is to use LVPECL flip-flops to sample the DUT and
>> reference clocks, convert the differential outputs to CMOS and feed the
>> FPGA inputs from that. Yes you loose AM noise riding on top of the
>> square wave, but is that really necessary for just square wave phase
>> noise measurements?
>
> Are the FPGA inputs low enough noise for that? With an ADC the time
> resolution is a combination of clock noise and input noise, for most high
> quality ADC the effective time resolution you can achieve by analyzing the
> output data stream is much higher than the resolution of the clock period.
> Can you achieve similar with just a single bit quantizer based on the FPGA
> CMOS inputs?
>
>
BC
Bob Camp
Mon, Jun 13, 2016 7:51 PM
Hi
The ECL inputs will be about 20 db more noisy than the CMOS inputs.
Some phase noise math:
The reference for phase noise is one radian. Yes, that seems a bit odd, but it’s phase modulation so that is the way it works.
If you are looking at a waveform with a period of 100 ns, your “one radian” will be about 15.9 ns. The “signal” you are after is (say)
100 db down from 15.9 ns.
Bob
On Jun 13, 2016, at 12:54 PM, John Swenson johnswenson1@comcast.net wrote:
The sampling will be done by a set of ECL flops. The FPGA is reading the already sampled ECL outputs. (with ECL to CMOS converters) I'm using a hex ECL register with one clock input for all six flops,
The ECL input circuit is a differential amplifier, I will be feeding the CMOS level input to one side and the other side will be a very low noise reference voltage set to half the CMOS voltage (1.65V for 3.3V square wave).
I really don't know the input noise of that differential amp, but it is probably much better than a normal CMOS input. I guess I will find out!
The particular chip says it has a max of 100fs additive jitter on the output from the input clock. But that is output jitter, I don't really care about output jitter, it is sampling jitter that is important here, I'm not sure how those two correlate.
John S.
On 6/13/2016 6:28 AM, Chris Caudle wrote:
On Sun, June 12, 2016 10:50 pm, John Swenson wrote:
I'm just doing phase noise measurements of digital clocks (square waves)
so it seems to me I don't need some of the circuitry in the TimePod, in
particular the digitally controlled RF attenuators and the ADCs
themselves. My idea is to use LVPECL flip-flops to sample the DUT and
reference clocks, convert the differential outputs to CMOS and feed the
FPGA inputs from that. Yes you loose AM noise riding on top of the
square wave, but is that really necessary for just square wave phase
noise measurements?
Are the FPGA inputs low enough noise for that? With an ADC the time
resolution is a combination of clock noise and input noise, for most high
quality ADC the effective time resolution you can achieve by analyzing the
output data stream is much higher than the resolution of the clock period.
Can you achieve similar with just a single bit quantizer based on the FPGA
CMOS inputs?
Hi
The ECL inputs will be about 20 db more noisy than the CMOS inputs.
Some phase noise math:
The reference for phase noise is one radian. Yes, that seems a bit odd, but it’s phase modulation so that is the way it works.
If you are looking at a waveform with a period of 100 ns, your “one radian” will be about 15.9 ns. The “signal” you are after is (say)
100 db down from 15.9 ns.
Bob
> On Jun 13, 2016, at 12:54 PM, John Swenson <johnswenson1@comcast.net> wrote:
>
> The sampling will be done by a set of ECL flops. The FPGA is reading the already sampled ECL outputs. (with ECL to CMOS converters) I'm using a hex ECL register with one clock input for all six flops,
>
> The ECL input circuit is a differential amplifier, I will be feeding the CMOS level input to one side and the other side will be a very low noise reference voltage set to half the CMOS voltage (1.65V for 3.3V square wave).
>
> I really don't know the input noise of that differential amp, but it is probably much better than a normal CMOS input. I guess I will find out!
>
> The particular chip says it has a max of 100fs additive jitter on the output from the input clock. But that is output jitter, I don't really care about output jitter, it is sampling jitter that is important here, I'm not sure how those two correlate.
>
> John S.
>
> On 6/13/2016 6:28 AM, Chris Caudle wrote:
>> On Sun, June 12, 2016 10:50 pm, John Swenson wrote:
>>> I'm just doing phase noise measurements of digital clocks (square waves)
>>> so it seems to me I don't need some of the circuitry in the TimePod, in
>>> particular the digitally controlled RF attenuators and the ADCs
>>> themselves. My idea is to use LVPECL flip-flops to sample the DUT and
>>> reference clocks, convert the differential outputs to CMOS and feed the
>>> FPGA inputs from that. Yes you loose AM noise riding on top of the
>>> square wave, but is that really necessary for just square wave phase
>>> noise measurements?
>>
>> Are the FPGA inputs low enough noise for that? With an ADC the time
>> resolution is a combination of clock noise and input noise, for most high
>> quality ADC the effective time resolution you can achieve by analyzing the
>> output data stream is much higher than the resolution of the clock period.
>> Can you achieve similar with just a single bit quantizer based on the FPGA
>> CMOS inputs?
>>
>>
>
> _______________________________________________
> time-nuts mailing list -- time-nuts@febo.com
> To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts
> and follow the instructions there.
BG
Bruce Griffiths
Mon, Jun 13, 2016 10:59 PM
In order to extract useful information with a 1 bit ADC, the signal transition region needs to be adequately sampled. Issues such as metastability need to be addressed to ensure that useful phase noise noise data can be extracted.
There is some evidence (from NIST and elsewhere) that ECL can have lower phase noise than CMOS at low offset frequencies.
Bruce
On Monday, 13 June 2016 8:12 PM, Bruce Griffiths <bruce.griffiths@xtra.co.nz> wrote:
Adjusting the sampling clock frequency so that is neither a harmonic nor a harmonic of a subharmonic of either of the clock frequencies being compared ensures that each clock waveform isnt repeatedly sampled at a small set of points.i.e.
fsample != (m/n)*ftest
andfsample != (p/q)*freference
where m,n,p,q are integers.
When using a dual reference the difference between the frequencies of the pair of reference sources should be significantly less than the lowest offset frequency of interest.
Bruce
On Monday, 13 June 2016 6:00 PM, John Swenson johnswenson1@comcast.net wrote:
Hi TimeNuts, this is my first post to this list, I've been reading it
for years but haven't needed to post, now I'm starting a project and
need some advice.
I need to do a bunch of phase noise measurements but can't afford the
"big guys", the TimePod seems perfect and since the schematic has been
published I decided I would try my hand at making my own version.
I'm just doing phase noise measurements of digital clocks (square waves)
so it seems to me I don't need some of the circuitry in the TimePod, in
particular the digitally controlled RF attenuators and the ADCs
themselves. My idea is to use LVPECL flip-flops to sample the DUT and
reference clocks, convert the differential outputs to CMOS and feed the
FPGA inputs from that. Yes you loose AM noise riding on top of the
square wave, but is that really necessary for just square wave phase
noise measurements?
For a first pass cheap and dirty version of this I was planning on using
the LVPECL version of the Crystek 575 for the sample clock, will this
work? The TimePod schematic shows a VTUNE signal fed to the OCXO, if I
don't use that is something going to break? In other words will timelab
try and tweak the sample freaquency and get confused when nothing happens?
I plan on using the 2 reference clock measurement technique, but have a
couple questions about this. In the TimePod ch 0 and 2 are the input,
with separate jacks available. The "ref" input goes to ch 1 and 3. So it
looks like the two references have to go to 0 and 2 and the DUT to 1 and
3, even though that puts the references on the "input" and the DUT on
the "reference". Do you need to do anything special in TimeLab to
support this or does it automatically support it? Since I am doing my
own hardware and have four independent inputs do I do the same thing
(ref clocks on 0 and 2 and DUT on 1 and 3) or put the refs on 1 and 3
and the DUT on 0 and 2?
Any thoughts?
Thanks,
John S.
time-nuts mailing list -- time-nuts@febo.com
To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts
and follow the instructions there.
time-nuts mailing list -- time-nuts@febo.com
To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts
and follow the instructions there.
In order to extract useful information with a 1 bit ADC, the signal transition region needs to be adequately sampled. Issues such as metastability need to be addressed to ensure that useful phase noise noise data can be extracted.
There is some evidence (from NIST and elsewhere) that ECL can have lower phase noise than CMOS at low offset frequencies.
Bruce
On Monday, 13 June 2016 8:12 PM, Bruce Griffiths <bruce.griffiths@xtra.co.nz> wrote:
Adjusting the sampling clock frequency so that is neither a harmonic nor a harmonic of a subharmonic of either of the clock frequencies being compared ensures that each clock waveform isnt repeatedly sampled at a small set of points.i.e.
fsample != (m/n)*ftest
andfsample != (p/q)*freference
where m,n,p,q are integers.
When using a dual reference the difference between the frequencies of the pair of reference sources should be significantly less than the lowest offset frequency of interest.
Bruce
On Monday, 13 June 2016 6:00 PM, John Swenson <johnswenson1@comcast.net> wrote:
Hi TimeNuts, this is my first post to this list, I've been reading it
for years but haven't needed to post, now I'm starting a project and
need some advice.
I need to do a bunch of phase noise measurements but can't afford the
"big guys", the TimePod seems perfect and since the schematic has been
published I decided I would try my hand at making my own version.
I'm just doing phase noise measurements of digital clocks (square waves)
so it seems to me I don't need some of the circuitry in the TimePod, in
particular the digitally controlled RF attenuators and the ADCs
themselves. My idea is to use LVPECL flip-flops to sample the DUT and
reference clocks, convert the differential outputs to CMOS and feed the
FPGA inputs from that. Yes you loose AM noise riding on top of the
square wave, but is that really necessary for just square wave phase
noise measurements?
For a first pass cheap and dirty version of this I was planning on using
the LVPECL version of the Crystek 575 for the sample clock, will this
work? The TimePod schematic shows a VTUNE signal fed to the OCXO, if I
don't use that is something going to break? In other words will timelab
try and tweak the sample freaquency and get confused when nothing happens?
I plan on using the 2 reference clock measurement technique, but have a
couple questions about this. In the TimePod ch 0 and 2 are the input,
with separate jacks available. The "ref" input goes to ch 1 and 3. So it
looks like the two references have to go to 0 and 2 and the DUT to 1 and
3, even though that puts the references on the "input" and the DUT on
the "reference". Do you need to do anything special in TimeLab to
support this or does it automatically support it? Since I am doing my
own hardware and have four independent inputs do I do the same thing
(ref clocks on 0 and 2 and DUT on 1 and 3) or put the refs on 1 and 3
and the DUT on 0 and 2?
Any thoughts?
Thanks,
John S.
_______________________________________________
time-nuts mailing list -- time-nuts@febo.com
To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts
and follow the instructions there.
_______________________________________________
time-nuts mailing list -- time-nuts@febo.com
To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts
and follow the instructions there.
BC
Bob Camp
Mon, Jun 13, 2016 11:51 PM
Hi
….. but …. The ECL inputs to an FPGA rarely do have lower noise.
Bob
On Jun 13, 2016, at 6:59 PM, Bruce Griffiths bruce.griffiths@xtra.co.nz wrote:
In order to extract useful information with a 1 bit ADC, the signal transition region needs to be adequately sampled. Issues such as metastability need to be addressed to ensure that useful phase noise noise data can be extracted.
There is some evidence (from NIST and elsewhere) that ECL can have lower phase noise than CMOS at low offset frequencies.
Bruce
On Monday, 13 June 2016 8:12 PM, Bruce Griffiths <bruce.griffiths@xtra.co.nz> wrote:
Adjusting the sampling clock frequency so that is neither a harmonic nor a harmonic of a subharmonic of either of the clock frequencies being compared ensures that each clock waveform isnt repeatedly sampled at a small set of points.i.e.
fsample != (m/n)*ftest
andfsample != (p/q)*freference
where m,n,p,q are integers.
When using a dual reference the difference between the frequencies of the pair of reference sources should be significantly less than the lowest offset frequency of interest.
Bruce
On Monday, 13 June 2016 6:00 PM, John Swenson <johnswenson1@comcast.net> wrote:
Hi TimeNuts, this is my first post to this list, I've been reading it
for years but haven't needed to post, now I'm starting a project and
need some advice.
I need to do a bunch of phase noise measurements but can't afford the
"big guys", the TimePod seems perfect and since the schematic has been
published I decided I would try my hand at making my own version.
I'm just doing phase noise measurements of digital clocks (square waves)
so it seems to me I don't need some of the circuitry in the TimePod, in
particular the digitally controlled RF attenuators and the ADCs
themselves. My idea is to use LVPECL flip-flops to sample the DUT and
reference clocks, convert the differential outputs to CMOS and feed the
FPGA inputs from that. Yes you loose AM noise riding on top of the
square wave, but is that really necessary for just square wave phase
noise measurements?
For a first pass cheap and dirty version of this I was planning on using
the LVPECL version of the Crystek 575 for the sample clock, will this
work? The TimePod schematic shows a VTUNE signal fed to the OCXO, if I
don't use that is something going to break? In other words will timelab
try and tweak the sample freaquency and get confused when nothing happens?
I plan on using the 2 reference clock measurement technique, but have a
couple questions about this. In the TimePod ch 0 and 2 are the input,
with separate jacks available. The "ref" input goes to ch 1 and 3. So it
looks like the two references have to go to 0 and 2 and the DUT to 1 and
3, even though that puts the references on the "input" and the DUT on
the "reference". Do you need to do anything special in TimeLab to
support this or does it automatically support it? Since I am doing my
own hardware and have four independent inputs do I do the same thing
(ref clocks on 0 and 2 and DUT on 1 and 3) or put the refs on 1 and 3
and the DUT on 0 and 2?
Any thoughts?
Thanks,
John S.
time-nuts mailing list -- time-nuts@febo.com
To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts
and follow the instructions there.
time-nuts mailing list -- time-nuts@febo.com
To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts
and follow the instructions there.
time-nuts mailing list -- time-nuts@febo.com
To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts
and follow the instructions there.
Hi
….. but …. The ECL inputs to an FPGA rarely do have lower noise.
Bob
> On Jun 13, 2016, at 6:59 PM, Bruce Griffiths <bruce.griffiths@xtra.co.nz> wrote:
>
> In order to extract useful information with a 1 bit ADC, the signal transition region needs to be adequately sampled. Issues such as metastability need to be addressed to ensure that useful phase noise noise data can be extracted.
> There is some evidence (from NIST and elsewhere) that ECL can have lower phase noise than CMOS at low offset frequencies.
> Bruce
>
>
> On Monday, 13 June 2016 8:12 PM, Bruce Griffiths <bruce.griffiths@xtra.co.nz> wrote:
>
>
> Adjusting the sampling clock frequency so that is neither a harmonic nor a harmonic of a subharmonic of either of the clock frequencies being compared ensures that each clock waveform isnt repeatedly sampled at a small set of points.i.e.
> fsample != (m/n)*ftest
> andfsample != (p/q)*freference
> where m,n,p,q are integers.
> When using a dual reference the difference between the frequencies of the pair of reference sources should be significantly less than the lowest offset frequency of interest.
> Bruce
>
>
> On Monday, 13 June 2016 6:00 PM, John Swenson <johnswenson1@comcast.net> wrote:
>
>
> Hi TimeNuts, this is my first post to this list, I've been reading it
> for years but haven't needed to post, now I'm starting a project and
> need some advice.
>
> I need to do a bunch of phase noise measurements but can't afford the
> "big guys", the TimePod seems perfect and since the schematic has been
> published I decided I would try my hand at making my own version.
>
> I'm just doing phase noise measurements of digital clocks (square waves)
> so it seems to me I don't need some of the circuitry in the TimePod, in
> particular the digitally controlled RF attenuators and the ADCs
> themselves. My idea is to use LVPECL flip-flops to sample the DUT and
> reference clocks, convert the differential outputs to CMOS and feed the
> FPGA inputs from that. Yes you loose AM noise riding on top of the
> square wave, but is that really necessary for just square wave phase
> noise measurements?
>
> For a first pass cheap and dirty version of this I was planning on using
> the LVPECL version of the Crystek 575 for the sample clock, will this
> work? The TimePod schematic shows a VTUNE signal fed to the OCXO, if I
> don't use that is something going to break? In other words will timelab
> try and tweak the sample freaquency and get confused when nothing happens?
>
> I plan on using the 2 reference clock measurement technique, but have a
> couple questions about this. In the TimePod ch 0 and 2 are the input,
> with separate jacks available. The "ref" input goes to ch 1 and 3. So it
> looks like the two references have to go to 0 and 2 and the DUT to 1 and
> 3, even though that puts the references on the "input" and the DUT on
> the "reference". Do you need to do anything special in TimeLab to
> support this or does it automatically support it? Since I am doing my
> own hardware and have four independent inputs do I do the same thing
> (ref clocks on 0 and 2 and DUT on 1 and 3) or put the refs on 1 and 3
> and the DUT on 0 and 2?
>
> Any thoughts?
>
> Thanks,
>
> John S.
> _______________________________________________
> time-nuts mailing list -- time-nuts@febo.com
> To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts
> and follow the instructions there.
>
>
>
> _______________________________________________
> time-nuts mailing list -- time-nuts@febo.com
> To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts
> and follow the instructions there.
>
>
>
> _______________________________________________
> time-nuts mailing list -- time-nuts@febo.com
> To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts
> and follow the instructions there.
CC
Chris Caudle
Tue, Jun 14, 2016 1:28 AM
On Mon, June 13, 2016 6:51 pm, Bob Camp wrote:
... The ECL inputs to an FPGA rarely do have lower noise.
I was confused about that at first, the original poster was using external
ECL receivers for sampling, but had CMOS outputs to transmit the data to
the FPGA.
That sounds to me like a one bit quantizer, which has approximately 6dB
dynamic range (neglecting for the moment things such as non-linearity and
aliasing). I don't see how you get any decent resolution of where the
edge transition actually occurs.
--
Chris Caudle
On Mon, June 13, 2016 6:51 pm, Bob Camp wrote:
> ... The ECL inputs to an FPGA rarely do have lower noise.
I was confused about that at first, the original poster was using external
ECL receivers for sampling, but had CMOS outputs to transmit the data to
the FPGA.
That sounds to me like a one bit quantizer, which has approximately 6dB
dynamic range (neglecting for the moment things such as non-linearity and
aliasing). I don't see how you get any decent resolution of where the
edge transition actually occurs.
--
Chris Caudle
JS
John Swenson
Tue, Jun 14, 2016 1:35 AM
But it is a separate ECL hex flip-flop chip fed by its own ultra low
noise regulator, not going directly into the FPGA.
John S.
On 6/13/2016 4:51 PM, Bob Camp wrote:
Hi
….. but …. The ECL inputs to an FPGA rarely do have lower noise.
Bob
On Jun 13, 2016, at 6:59 PM, Bruce Griffiths bruce.griffiths@xtra.co.nz wrote:
In order to extract useful information with a 1 bit ADC, the signal transition region needs to be adequately sampled. Issues such as metastability need to be addressed to ensure that useful phase noise noise data can be extracted.
There is some evidence (from NIST and elsewhere) that ECL can have lower phase noise than CMOS at low offset frequencies.
Bruce
On Monday, 13 June 2016 8:12 PM, Bruce Griffiths <bruce.griffiths@xtra.co.nz> wrote:
Adjusting the sampling clock frequency so that is neither a harmonic nor a harmonic of a subharmonic of either of the clock frequencies being compared ensures that each clock waveform isnt repeatedly sampled at a small set of points.i.e.
fsample != (m/n)*ftest
andfsample != (p/q)*freference
where m,n,p,q are integers.
When using a dual reference the difference between the frequencies of the pair of reference sources should be significantly less than the lowest offset frequency of interest.
Bruce
On Monday, 13 June 2016 6:00 PM, John Swenson <johnswenson1@comcast.net> wrote:
Hi TimeNuts, this is my first post to this list, I've been reading it
for years but haven't needed to post, now I'm starting a project and
need some advice.
I need to do a bunch of phase noise measurements but can't afford the
"big guys", the TimePod seems perfect and since the schematic has been
published I decided I would try my hand at making my own version.
I'm just doing phase noise measurements of digital clocks (square waves)
so it seems to me I don't need some of the circuitry in the TimePod, in
particular the digitally controlled RF attenuators and the ADCs
themselves. My idea is to use LVPECL flip-flops to sample the DUT and
reference clocks, convert the differential outputs to CMOS and feed the
FPGA inputs from that. Yes you loose AM noise riding on top of the
square wave, but is that really necessary for just square wave phase
noise measurements?
For a first pass cheap and dirty version of this I was planning on using
the LVPECL version of the Crystek 575 for the sample clock, will this
work? The TimePod schematic shows a VTUNE signal fed to the OCXO, if I
don't use that is something going to break? In other words will timelab
try and tweak the sample freaquency and get confused when nothing happens?
I plan on using the 2 reference clock measurement technique, but have a
couple questions about this. In the TimePod ch 0 and 2 are the input,
with separate jacks available. The "ref" input goes to ch 1 and 3. So it
looks like the two references have to go to 0 and 2 and the DUT to 1 and
3, even though that puts the references on the "input" and the DUT on
the "reference". Do you need to do anything special in TimeLab to
support this or does it automatically support it? Since I am doing my
own hardware and have four independent inputs do I do the same thing
(ref clocks on 0 and 2 and DUT on 1 and 3) or put the refs on 1 and 3
and the DUT on 0 and 2?
Any thoughts?
Thanks,
John S.
time-nuts mailing list -- time-nuts@febo.com
To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts
and follow the instructions there.
time-nuts mailing list -- time-nuts@febo.com
To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts
and follow the instructions there.
time-nuts mailing list -- time-nuts@febo.com
To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts
and follow the instructions there.
But it is a separate ECL hex flip-flop chip fed by its own ultra low
noise regulator, not going directly into the FPGA.
John S.
On 6/13/2016 4:51 PM, Bob Camp wrote:
> Hi
>
> ….. but …. The ECL inputs to an FPGA rarely do have lower noise.
>
> Bob
>
>> On Jun 13, 2016, at 6:59 PM, Bruce Griffiths <bruce.griffiths@xtra.co.nz> wrote:
>>
>> In order to extract useful information with a 1 bit ADC, the signal transition region needs to be adequately sampled. Issues such as metastability need to be addressed to ensure that useful phase noise noise data can be extracted.
>> There is some evidence (from NIST and elsewhere) that ECL can have lower phase noise than CMOS at low offset frequencies.
>> Bruce
>>
>>
>> On Monday, 13 June 2016 8:12 PM, Bruce Griffiths <bruce.griffiths@xtra.co.nz> wrote:
>>
>>
>> Adjusting the sampling clock frequency so that is neither a harmonic nor a harmonic of a subharmonic of either of the clock frequencies being compared ensures that each clock waveform isnt repeatedly sampled at a small set of points.i.e.
>> fsample != (m/n)*ftest
>> andfsample != (p/q)*freference
>> where m,n,p,q are integers.
>> When using a dual reference the difference between the frequencies of the pair of reference sources should be significantly less than the lowest offset frequency of interest.
>> Bruce
>>
>>
>> On Monday, 13 June 2016 6:00 PM, John Swenson <johnswenson1@comcast.net> wrote:
>>
>>
>> Hi TimeNuts, this is my first post to this list, I've been reading it
>> for years but haven't needed to post, now I'm starting a project and
>> need some advice.
>>
>> I need to do a bunch of phase noise measurements but can't afford the
>> "big guys", the TimePod seems perfect and since the schematic has been
>> published I decided I would try my hand at making my own version.
>>
>> I'm just doing phase noise measurements of digital clocks (square waves)
>> so it seems to me I don't need some of the circuitry in the TimePod, in
>> particular the digitally controlled RF attenuators and the ADCs
>> themselves. My idea is to use LVPECL flip-flops to sample the DUT and
>> reference clocks, convert the differential outputs to CMOS and feed the
>> FPGA inputs from that. Yes you loose AM noise riding on top of the
>> square wave, but is that really necessary for just square wave phase
>> noise measurements?
>>
>> For a first pass cheap and dirty version of this I was planning on using
>> the LVPECL version of the Crystek 575 for the sample clock, will this
>> work? The TimePod schematic shows a VTUNE signal fed to the OCXO, if I
>> don't use that is something going to break? In other words will timelab
>> try and tweak the sample freaquency and get confused when nothing happens?
>>
>> I plan on using the 2 reference clock measurement technique, but have a
>> couple questions about this. In the TimePod ch 0 and 2 are the input,
>> with separate jacks available. The "ref" input goes to ch 1 and 3. So it
>> looks like the two references have to go to 0 and 2 and the DUT to 1 and
>> 3, even though that puts the references on the "input" and the DUT on
>> the "reference". Do you need to do anything special in TimeLab to
>> support this or does it automatically support it? Since I am doing my
>> own hardware and have four independent inputs do I do the same thing
>> (ref clocks on 0 and 2 and DUT on 1 and 3) or put the refs on 1 and 3
>> and the DUT on 0 and 2?
>>
>> Any thoughts?
>>
>> Thanks,
>>
>> John S.
>> _______________________________________________
>> time-nuts mailing list -- time-nuts@febo.com
>> To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts
>> and follow the instructions there.
>>
>>
>>
>> _______________________________________________
>> time-nuts mailing list -- time-nuts@febo.com
>> To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts
>> and follow the instructions there.
>>
>>
>>
>> _______________________________________________
>> time-nuts mailing list -- time-nuts@febo.com
>> To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts
>> and follow the instructions there.
>
> _______________________________________________
> time-nuts mailing list -- time-nuts@febo.com
> To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts
> and follow the instructions there.
>
