DIY TimePod
The subsequent all digital mixdown and low pass filtering, if done correctly, will increase the resolution provided that the signal and reference periods are uniformly sampled at a sufficient equivalent number of points. But with a starting point some 70dB or more behind an ADC, the system noise floor wont be particularly low.
Bruce
On Tuesday, 14 June 2016 1:28 PM, Chris Caudle <chris@chriscaudle.org> wrote:
On Mon, June 13, 2016 6:51 pm, Bob Camp wrote:
... The ECL inputs to an FPGA rarely do have lower noise.
I was confused about that at first, the original poster was using external
ECL receivers for sampling, but had CMOS outputs to transmit the data to
the FPGA.
That sounds to me like a one bit quantizer, which has approximately 6dB
dynamic range (neglecting for the moment things such as non-linearity and
aliasing). I don't see how you get any decent resolution of where the
edge transition actually occurs.
--
Chris Caudle
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If the quantisation noise is random and spread uniformly over the Nyquist bandwidth (~40MHz??) then the noise floor is about -82dBc/Hz.If a pair of independent quantisers is employed then by using cross correlation techniques it should be possible to lower the system noise floor to -100dBC/Hz or less.
The problem lies in ensuring that the quantisation noise is actually random..With a high resolution RF ADC internal noise is usually sufficient (>= 1 lsb)) to ensure this.
Bruce
On Tuesday, 14 June 2016 2:11 PM, Bruce Griffiths <bruce.griffiths@xtra..co.nz> wrote:
The subsequent all digital mixdown and low pass filtering, if done correctly, will increase the resolution provided that the signal and reference periods are uniformly sampled at a sufficient equivalent number of points. But with a starting point some 70dB or more behind an ADC, the system noise floor wont be particularly low.
Bruce
On Tuesday, 14 June 2016 1:28 PM, Chris Caudle <chris@chriscaudle.org> wrote:
On Mon, June 13, 2016 6:51 pm, Bob Camp wrote:
... The ECL inputs to an FPGA rarely do have lower noise.
I was confused about that at first, the original poster was using external
ECL receivers for sampling, but had CMOS outputs to transmit the data to
the FPGA.
That sounds to me like a one bit quantizer, which has approximately 6dB
dynamic range (neglecting for the moment things such as non-linearity and
aliasing). I don't see how you get any decent resolution of where the
edge transition actually occurs.
--
Chris Caudle
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On Mon, June 13, 2016 9:38 pm, Bruce Griffiths wrote:
If the quantisation noise is random and spread uniformly over the Nyquist
bandwidth (~40MHz??) then the noise floor is about -82dBc/Hz.
How do you spread the quantization noise randomly with a one bit
quantizer? I'm mostly familiar with single bit quanitizers in the context
of audio range delta-sigma converters where the quantizer is in a feedback
loop to move most of the noise to a higher frequency range. That also
requires a clock much higher than the minimum nyquist requirement.
Maybe I need to see a block diagram of what is being described. Where is
the clock for the ECL flip-flop generated? I don't recall seeing a
description of what the effective sample rate will be, or the highest
clock signal accepted for analysis.
With a high resolution RF ADC internal noise is usually sufficient
(>= 1 lsb)) to ensure this.
Can't really dither to >= 1lsb when lsb=msb (single bit quantizer).
--
Chris Caudle
The idea here is around a 80MHz sample clock with a maximum input/ref
signal of around 25MHz. This is based on the TimePod with ADCs, which is
supposed to work with square waves. Its is using a 77MHz clock if I
remember correctly, so somewhere in the neighborhood of 12-13 ns per sample.
When you feed a square wave into this you have several samples at say
50, then it jumps to 50,000 stays there for several samples, then jumps
down to 50 again. This still seems like a binary sample. The difference
is that every now and then the sample hits during a ramptime of the
square wave and will give some intermediate value, is this enough of a
difference to invalidate the concept of a binary sample?
Or is the difference that the ADC won't stay at 50, but will be bouncing
around say between 45 and 55 when the square wave is low and this noise
makes it work? If that is the case then wouldn't a longer measurement
time do essentially the same thing with slight variations of timing of
the edge due to the noise in the binary sampler?
John S.
On 6/13/2016 8:17 PM, Chris Caudle wrote:
On Mon, June 13, 2016 9:38 pm, Bruce Griffiths wrote:
If the quantisation noise is random and spread uniformly over the Nyquist
bandwidth (~40MHz??) then the noise floor is about -82dBc/Hz.
How do you spread the quantization noise randomly with a one bit
quantizer? I'm mostly familiar with single bit quanitizers in the context
of audio range delta-sigma converters where the quantizer is in a feedback
loop to move most of the noise to a higher frequency range. That also
requires a clock much higher than the minimum nyquist requirement.
Maybe I need to see a block diagram of what is being described. Where is
the clock for the ECL flip-flop generated? I don't recall seeing a
description of what the effective sample rate will be, or the highest
clock signal accepted for analysis.
With a high resolution RF ADC internal noise is usually sufficient
(>= 1 lsb)) to ensure this.
Can't really dither to >= 1lsb when lsb=msb (single bit quantizer).
Examples of using 1-2 bit digitisers are radio astronomy receivers or some GPS receivers where the signal is essentially noise or the signal is buried in noise.
If this were to be useful, then at least 2 channels per signal, each channel having its own independent noise source, would be required.
Bruce
On Tuesday, 14 June 2016 6:01 PM, Chris Caudle <chris@chriscaudle.org> wrote:
On Mon, June 13, 2016 9:38 pm, Bruce Griffiths wrote:
If the quantisation noise is random and spread uniformly over the Nyquist
bandwidth (~40MHz??) then the noise floor is about -82dBc/Hz.
How do you spread the quantization noise randomly with a one bit
quantizer? I'm mostly familiar with single bit quanitizers in the context
of audio range delta-sigma converters where the quantizer is in a feedback
loop to move most of the noise to a higher frequency range. That also
requires a clock much higher than the minimum nyquist requirement.
Maybe I need to see a block diagram of what is being described. Where is
the clock for the ECL flip-flop generated? I don't recall seeing a
description of what the effective sample rate will be, or the highest
clock signal accepted for analysis.
With a high resolution RF ADC internal noise is usually sufficient
(>= 1 lsb)) to ensure this.
Can't really dither to >= 1lsb when lsb=msb (single bit quantizer).
--
Chris Caudle
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HI
If you wire up a CMOS gate and an ECL gate, check each for phase noise on the output, the CMOS gate
will have better phase noise. That is true comparing inputs on FPGA to FPGA or comparing chip to chop.
The FPGA inputs will be noisier than the dedicated gates in both cases.
Bob
On Jun 13, 2016, at 9:35 PM, John Swenson johnswenson1@comcast.net wrote:
But it is a separate ECL hex flip-flop chip fed by its own ultra low noise regulator, not going directly into the FPGA.
John S.
On 6/13/2016 4:51 PM, Bob Camp wrote:
Hi
….. but …. The ECL inputs to an FPGA rarely do have lower noise.
Bob
On Jun 13, 2016, at 6:59 PM, Bruce Griffiths bruce.griffiths@xtra.co.nz wrote:
In order to extract useful information with a 1 bit ADC, the signal transition region needs to be adequately sampled. Issues such as metastability need to be addressed to ensure that useful phase noise noise data can be extracted.
There is some evidence (from NIST and elsewhere) that ECL can have lower phase noise than CMOS at low offset frequencies.
Bruce
On Monday, 13 June 2016 8:12 PM, Bruce Griffiths <bruce.griffiths@xtra.co.nz> wrote:
Adjusting the sampling clock frequency so that is neither a harmonic nor a harmonic of a subharmonic of either of the clock frequencies being compared ensures that each clock waveform isnt repeatedly sampled at a small set of points.i.e.
fsample != (m/n)*ftest
andfsample != (p/q)*freference
where m,n,p,q are integers.
When using a dual reference the difference between the frequencies of the pair of reference sources should be significantly less than the lowest offset frequency of interest.
Bruce
On Monday, 13 June 2016 6:00 PM, John Swenson <johnswenson1@comcast.net> wrote:
Hi TimeNuts, this is my first post to this list, I've been reading it
for years but haven't needed to post, now I'm starting a project and
need some advice.
I need to do a bunch of phase noise measurements but can't afford the
"big guys", the TimePod seems perfect and since the schematic has been
published I decided I would try my hand at making my own version.
I'm just doing phase noise measurements of digital clocks (square waves)
so it seems to me I don't need some of the circuitry in the TimePod, in
particular the digitally controlled RF attenuators and the ADCs
themselves. My idea is to use LVPECL flip-flops to sample the DUT and
reference clocks, convert the differential outputs to CMOS and feed the
FPGA inputs from that. Yes you loose AM noise riding on top of the
square wave, but is that really necessary for just square wave phase
noise measurements?
For a first pass cheap and dirty version of this I was planning on using
the LVPECL version of the Crystek 575 for the sample clock, will this
work? The TimePod schematic shows a VTUNE signal fed to the OCXO, if I
don't use that is something going to break? In other words will timelab
try and tweak the sample freaquency and get confused when nothing happens?
I plan on using the 2 reference clock measurement technique, but have a
couple questions about this. In the TimePod ch 0 and 2 are the input,
with separate jacks available. The "ref" input goes to ch 1 and 3. So it
looks like the two references have to go to 0 and 2 and the DUT to 1 and
3, even though that puts the references on the "input" and the DUT on
the "reference". Do you need to do anything special in TimeLab to
support this or does it automatically support it? Since I am doing my
own hardware and have four independent inputs do I do the same thing
(ref clocks on 0 and 2 and DUT on 1 and 3) or put the refs on 1 and 3
and the DUT on 0 and 2?
Any thoughts?
Thanks,
John S.
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To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts
and follow the instructions there.
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To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts
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Hi
The input to the ADC is lowpass filtered. If you use a square wave it “sees” a more or less sine wave. If you are running
a very low frequency square wave, you can use an external lowpass filter. Since one channel is a reference, you may only
need one external lowpass filter.
Bob
On Jun 14, 2016, at 3:35 AM, John Swenson johnswenson1@comcast.net wrote:
The idea here is around a 80MHz sample clock with a maximum input/ref signal of around 25MHz. This is based on the TimePod with ADCs, which is supposed to work with square waves. Its is using a 77MHz clock if I remember correctly, so somewhere in the neighborhood of 12-13 ns per sample.
When you feed a square wave into this you have several samples at say 50, then it jumps to 50,000 stays there for several samples, then jumps down to 50 again. This still seems like a binary sample. The difference is that every now and then the sample hits during a ramptime of the square wave and will give some intermediate value, is this enough of a difference to invalidate the concept of a binary sample?
Or is the difference that the ADC won't stay at 50, but will be bouncing around say between 45 and 55 when the square wave is low and this noise makes it work? If that is the case then wouldn't a longer measurement time do essentially the same thing with slight variations of timing of the edge due to the noise in the binary sampler?
John S.
On 6/13/2016 8:17 PM, Chris Caudle wrote:
On Mon, June 13, 2016 9:38 pm, Bruce Griffiths wrote:
If the quantisation noise is random and spread uniformly over the Nyquist
bandwidth (~40MHz??) then the noise floor is about -82dBc/Hz.
How do you spread the quantization noise randomly with a one bit
quantizer? I'm mostly familiar with single bit quanitizers in the context
of audio range delta-sigma converters where the quantizer is in a feedback
loop to move most of the noise to a higher frequency range. That also
requires a clock much higher than the minimum nyquist requirement.
Maybe I need to see a block diagram of what is being described. Where is
the clock for the ECL flip-flop generated? I don't recall seeing a
description of what the effective sample rate will be, or the highest
clock signal accepted for analysis.
With a high resolution RF ADC internal noise is usually sufficient
(>= 1 lsb)) to ensure this.
Can't really dither to >= 1lsb when lsb=msb (single bit quantizer).
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and follow the instructions there.
On Tue, June 14, 2016 2:35 am, John Swenson wrote:
The idea here is around a 80MHz sample clock with a
maximum input/ref signal of around 25MHz.
Without some pretty steep low pass filtering that will violate the Nyquist
criterion (for 80MHz sample clock the input must be strictly limited to
less than 40MHz). You can't even get the first odd harmonic in of a 25MHz
square wave input.
This is based on the TimePod with ADCs, which is
supposed to work with square waves.
The ADC's would have a low pass filter in front. Think of it in terms of
the Shannon information capacity, the amount of information conveyed is
determined by the bandwidth and the signal to noise ratio. The bandwidth
is determined by the sample rate, the signal to noise ratio by the number
of (effective) bits of the ADC.
I forget which ADC someone mentioned recently as being in the TimePod.
Isn't it a 16 bit converter? So that is getting around 96dB integrated
signal to noise ratio per converter, and you are starting with 6dB.
When you feed a square wave into this you have several samples at say
50, then it jumps to 50,000 stays there for several samples, then jumps
down to 50 again.
The key thing you are missing which happens with a multi-bit ADC is that
the signal has a finite rise time, so it doesn't "jump" to 50,000, it has
a transition region where you get several samples of different values.
Those samples fit an infinite number of possible signals, but only one
signal which is limited to the Nyquist criterion bandwidth. Using those
samples and the knowledge of the system bandwidth you can interpolate
where the zero crossing must have been.
With a single bit quantizer (and no feedback to shape the noise), you get
very little information about the signal values in the transition region.
This still seems like a binary sample. The difference
is that every now and then the sample hits during a ramptime of the
square wave and will give some intermediate value,
No, every time you will sample during the transition, because the "square"
wave still has a finite rise time, and if you have properly bandwidth
limited the signal as required by the Nyquist sampling criterion (input
signal must be less than half the frequency of the sampling clock) then
you know what the upper limit on the rise time is.
--
Chris Caudle
Got it, I missed the 27 MHz low pass filter with 60 db attenuation. So
the ADC really is mostly seeing a sine wave.
I guess it's back to the drawing board and doing this with the filter
and the ADCs.
Thanks for setting me straight on this.
John S.
On 6/14/2016 3:01 PM, Chris Caudle wrote:
On Tue, June 14, 2016 2:35 am, John Swenson wrote:
The idea here is around a 80MHz sample clock with a
maximum input/ref signal of around 25MHz.
Without some pretty steep low pass filtering that will violate the Nyquist
criterion (for 80MHz sample clock the input must be strictly limited to
less than 40MHz). You can't even get the first odd harmonic in of a 25MHz
square wave input.
This is based on the TimePod with ADCs, which is
supposed to work with square waves.
The ADC's would have a low pass filter in front. Think of it in terms of
the Shannon information capacity, the amount of information conveyed is
determined by the bandwidth and the signal to noise ratio. The bandwidth
is determined by the sample rate, the signal to noise ratio by the number
of (effective) bits of the ADC.
I forget which ADC someone mentioned recently as being in the TimePod.
Isn't it a 16 bit converter? So that is getting around 96dB integrated
signal to noise ratio per converter, and you are starting with 6dB.
When you feed a square wave into this you have several samples at say
50, then it jumps to 50,000 stays there for several samples, then jumps
down to 50 again.
The key thing you are missing which happens with a multi-bit ADC is that
the signal has a finite rise time, so it doesn't "jump" to 50,000, it has
a transition region where you get several samples of different values.
Those samples fit an infinite number of possible signals, but only one
signal which is limited to the Nyquist criterion bandwidth. Using those
samples and the knowledge of the system bandwidth you can interpolate
where the zero crossing must have been.
With a single bit quantizer (and no feedback to shape the noise), you get
very little information about the signal values in the transition region.
This still seems like a binary sample. The difference
is that every now and then the sample hits during a ramptime of the
square wave and will give some intermediate value,
No, every time you will sample during the transition, because the "square"
wave still has a finite rise time, and if you have properly bandwidth
limited the signal as required by the Nyquist sampling criterion (input
signal must be less than half the frequency of the sampling clock) then
you know what the upper limit on the rise time is.
Hi
Since (in a sense) it’s a single frequency SDR, it very much looks at the fundamental sine wave
component.
Bob
On Jun 14, 2016, at 8:53 PM, John Swenson johnswenson1@comcast.net wrote:
Got it, I missed the 27 MHz low pass filter with 60 db attenuation. So the ADC really is mostly seeing a sine wave.
I guess it's back to the drawing board and doing this with the filter and the ADCs.
Thanks for setting me straight on this.
John S.
On 6/14/2016 3:01 PM, Chris Caudle wrote:
On Tue, June 14, 2016 2:35 am, John Swenson wrote:
The idea here is around a 80MHz sample clock with a
maximum input/ref signal of around 25MHz.
Without some pretty steep low pass filtering that will violate the Nyquist
criterion (for 80MHz sample clock the input must be strictly limited to
less than 40MHz). You can't even get the first odd harmonic in of a 25MHz
square wave input.
This is based on the TimePod with ADCs, which is
supposed to work with square waves.
The ADC's would have a low pass filter in front. Think of it in terms of
the Shannon information capacity, the amount of information conveyed is
determined by the bandwidth and the signal to noise ratio. The bandwidth
is determined by the sample rate, the signal to noise ratio by the number
of (effective) bits of the ADC.
I forget which ADC someone mentioned recently as being in the TimePod.
Isn't it a 16 bit converter? So that is getting around 96dB integrated
signal to noise ratio per converter, and you are starting with 6dB.
When you feed a square wave into this you have several samples at say
50, then it jumps to 50,000 stays there for several samples, then jumps
down to 50 again.
The key thing you are missing which happens with a multi-bit ADC is that
the signal has a finite rise time, so it doesn't "jump" to 50,000, it has
a transition region where you get several samples of different values.
Those samples fit an infinite number of possible signals, but only one
signal which is limited to the Nyquist criterion bandwidth. Using those
samples and the knowledge of the system bandwidth you can interpolate
where the zero crossing must have been.
With a single bit quantizer (and no feedback to shape the noise), you get
very little information about the signal values in the transition region.
This still seems like a binary sample. The difference
is that every now and then the sample hits during a ramptime of the
square wave and will give some intermediate value,
No, every time you will sample during the transition, because the "square"
wave still has a finite rise time, and if you have properly bandwidth
limited the signal as required by the Nyquist sampling criterion (input
signal must be less than half the frequency of the sampling clock) then
you know what the upper limit on the rise time is.
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