PLL performance?
Hi All,
I have built and tested a PLL circuit that will be used to generate a 1 MHz signal locked to a 0.5 HZ signal from a pendulum. (Details available upon request.)
The circuit is a classic 4046 generating the 1 MHz signal which is fed into a 2e6 digital divider which outputs 0.5 Hz which is fed back to the 4046 phase comparator (PC).
I take a 1 MHz signal from an HP 107A run through another 2e6 divider to generate a reference 0.5 Hz signal for the other 4046 PC input.
I tested this by feeding the 0.5 Hz output of the PLL into a "time-stamp counter" board which I built to go into an HP 3582A Data Acquisition unit. The TSC uses the 5 MHz signal from the HP 107A to feed a free-running 32-bit binary counter. The 0.5 Hz input latches the count value (on the rising edge of the signal), which is then logged.
See the attached diagram. The PLL under test is in the red box. (Not sure what the policy is here for attachments?)
If all was perfect I would get a string of values of 10,000,000 counts each, one every 2 seconds.
Over the course of one day the average reading is, in fact, 10e6, so the PLL looks to be working over "long" time scales.
The attached histogram plot shows the actual data for the 0.5 Hz signal, showing the distribution of deviations from 10e6 counts. This is almost a full day of data, about 40,000 readings.
The standard deviation for the data is about 55 counts.
The plot looks to my eye to be a nice Gaussian shape, so I assume that the deviations are caused mainly by (white?) noise. There does not look to be much other structure in the shape of the data. (Comments welcome.)
Sorry for the long introduction, there are some questions coming!
I have looked for information on the web about others who may have done this kind of PLL, but did not find much.
Does anyone know of any articles related to this?
If so, do you know what kind of performance they got?
What kind of statement could I make about the 'stability' of this circuit? Simplistically: a 'stability' of ~50 counts in 10e6 is ~5e-7?
By the way, this performance is WAY WAY beyond what I was expecting....
Cheers,
Scott
Hi. I did a 15728640Hz signal locked to a 7680Hz reference using a
74hct9046. It was ugly (I mean, individual trimming of the resistors...
I assembled 20 boards). Circuit behaves more like a FLL than a PLL (if
you look at both with an scope they never quite locks to each other),
but it works for the mean values (so long averages are ok, and that´s
what I was looking for). I didn´t measure stability, just tested each
board to see if they kept locked between (60,1128)Hz and (59,9128)Hz.
That was a pain. I think these 4046 and 9046 don´t work well when the
frequencies are too apart, but I can´t tell for sure. Not enough
experience with that.
Daniel
Em 20/03/2017 22:07, David Scott Coburn escreveu:
Hi All,
I have built and tested a PLL circuit that will be used to generate a 1 MHz signal locked to a 0.5 HZ signal from a pendulum. (Details available upon request.)
The circuit is a classic 4046 generating the 1 MHz signal which is fed into a 2e6 digital divider which outputs 0.5 Hz which is fed back to the 4046 phase comparator (PC).
I take a 1 MHz signal from an HP 107A run through another 2e6 divider to generate a reference 0.5 Hz signal for the other 4046 PC input.
I tested this by feeding the 0.5 Hz output of the PLL into a "time-stamp counter" board which I built to go into an HP 3582A Data Acquisition unit. The TSC uses the 5 MHz signal from the HP 107A to feed a free-running 32-bit binary counter. The 0.5 Hz input latches the count value (on the rising edge of the signal), which is then logged.
See the attached diagram. The PLL under test is in the red box. (Not sure what the policy is here for attachments?)
If all was perfect I would get a string of values of 10,000,000 counts each, one every 2 seconds.
Over the course of one day the average reading is, in fact, 10e6, so the PLL looks to be working over "long" time scales.
The attached histogram plot shows the actual data for the 0.5 Hz signal, showing the distribution of deviations from 10e6 counts. This is almost a full day of data, about 40,000 readings.
The standard deviation for the data is about 55 counts.
The plot looks to my eye to be a nice Gaussian shape, so I assume that the deviations are caused mainly by (white?) noise. There does not look to be much other structure in the shape of the data. (Comments welcome.)
Sorry for the long introduction, there are some questions coming!
I have looked for information on the web about others who may have done this kind of PLL, but did not find much.
Does anyone know of any articles related to this?
If so, do you know what kind of performance they got?
What kind of statement could I make about the 'stability' of this circuit? Simplistically: a 'stability' of ~50 counts in 10e6 is ~5e-7?
By the way, this performance is WAY WAY beyond what I was expecting....
Cheers,
Scott
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Hi, Scott. I rarely post here, but just noticed your post. I can open
the "PLL0.pdf" file, but the other files appears to be corrupted. Adobe
Acrobat Reader thinks it's not really a PDF file or it's corrupted. I'm
not ready to comment on the expected results yet, and would like to see
the histogram.
Are you using phase detector 1 or 2? What are the details for your loop
filter?
--
Bill Byrom N5BB
----- Original message -----
From: David Scott Coburn scotttt@optonline.net
To: time-nuts@febo.com
Subject: [time-nuts] PLL performance?
Date: Mon, 20 Mar 2017 21:07:03 -0400
Hi All,
I have built and tested a PLL circuit that will be used to generate a 1
MHz signal locked to a 0.5 HZ signal from a pendulum. (Details
available upon request.)
The circuit is a classic 4046 generating the 1 MHz signal which is fed
into a 2e6 digital divider which outputs 0.5 Hz which is fed back to the
4046 phase comparator (PC).
I take a 1 MHz signal from an HP 107A run through another 2e6 divider to
generate a reference 0.5 Hz signal for the other 4046 PC input.
I tested this by feeding the 0.5 Hz output of the PLL into a "time-stamp
counter" board which I built to go into an HP 3582A Data Acquisition
unit. The TSC uses the 5 MHz signal from the HP 107A to feed a
free-running 32-bit binary counter. The 0.5 Hz input latches the count
value (on the rising edge of the signal), which is then logged.
See the attached diagram. The PLL under test is in the red box. (Not
sure what the policy is here for attachments?)
If all was perfect I would get a string of values of 10,000,000 counts
each, one every 2 seconds.
Over the course of one day the average reading is, in fact, 10e6, so the
PLL looks to be working over "long" time scales.
The attached histogram plot shows the actual data for the 0.5 Hz signal,
showing the distribution of deviations from 10e6 counts. This is almost
a full day of data, about 40,000 readings.
The standard deviation for the data is about 55 counts.
The plot looks to my eye to be a nice Gaussian shape, so I assume that
the deviations are caused mainly by (white?) noise. There does not look
to be much other structure in the shape of the data. (Comments
welcome.)
Sorry for the long introduction, there are some questions coming!
I have looked for information on the web about others who may have done
this kind of PLL, but did not find much.
Does anyone know of any articles related to this?
If so, do you know what kind of performance they got?
What kind of statement could I make about the 'stability' of this
circuit? Simplistically: a 'stability' of ~50 counts in 10e6 is ~5e-7?
By the way, this performance is WAY WAY beyond what I was expecting....
Cheers,
Scott
time-nuts mailing list -- time-nuts@febo.com
To unsubscribe, go to
https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts
and follow the instructions there.
Email had 2 attachments:
- PLL0.pdf
22k (application/pdf) - histogram-utcday21613x.pdf
58k (application/pdf)
Second file successfully opened in Irfanview.
Three other PDF readers, including Adobe, could not open it.
Andy
Andy, Bill, et al.
Attached is a GIF version of Scott's (unreadable?) histogram-utcday21613x.pdf file.
/tvb
----- Original Message -----
From: "Andy" AI.egrps+tn@gmail.com
To: "Discussion of precise time and frequency measurement" time-nuts@febo.com
Sent: Tuesday, March 21, 2017 12:23 AM
Subject: Re: [time-nuts] PLL performance?
Second file successfully opened in Irfanview.
Three other PDF readers, including Adobe, could not open it.
Andy
Moin,
On Mon, 20 Mar 2017 21:07:03 -0400
David Scott Coburn scotttt@optonline.net wrote:
I have built and tested a PLL circuit that will be used to generate a 1 MHz
signal locked to a 0.5 HZ signal from a pendulum. (Details available upon
request.)
[...]
I tested this by feeding the 0.5 Hz output of the PLL into a "time-stamp
counter" board which I built to go into an HP 3582A Data Acquisition unit.
The TSC uses the 5 MHz signal from the HP 107A to feed a free-running 32-bit
binary counter. The 0.5 Hz input latches the count value (on the rising edge
of the signal), which is then logged.
The VCO in the 4046 is an odd mixture between a relaxation and an
delay line oscillator. It's stability is not that good (at least
not by modern standards). As such, your phase comparator frequency
of just 0.5Hz is too low for the 4046 to show its peak performance,
as it is basically free running for 2s before a slight correction
is applied. Usually the frequencies used for a 4046 are in the range
of 1kHz to 100kHz.
Alternatively, you can dissable the internal VCO (inhibit pin) and
use an external oscillator that is more stable. The VCXOs by Abracon
(ASVTX-*) are readily available and cheap enough. If you use a 20MHz
oscillator (e.g. ASVTX-09-20) divide the output first by 2 (using a
D-flipflop) and then by 10 (e.g. using 74LV161)
until you are at 1Hz, then use second D-flipflops to get to 0.5Hz.
This gives you 1MHz inbetween.
The standard deviation for the data is about 55 counts.
This means that your jitter (at 0.5Hz) is 11µs RMS.
The plot looks to my eye to be a nice Gaussian shape, so I assume that the
deviations are caused mainly by (white?) noise. There does not look to be
much other structure in the shape of the data. (Comments welcome.)
Yes, It looks very much Gauss shaped, it is very likely that this is
indeed a Gauss process, but to be sure (in a statistical sense) you
would need to do something like a qq-plot or similar to check,
whether it's actually a Gaus distribution (there are others that
look very similar). But for all practical purposes, that does not
really matter.
Please be aware that a noise process can be Gaussian and not be white.
E.g. 1/f-noise has a Gaussian distribution as well.
I have looked for information on the web about others who may have done this
kind of PLL, but did not find much.
Does anyone know of any articles related to this?
What information are you looking for?
If so, do you know what kind of performance they got?
Your performance seem's ok, but limited by the VCO of the 4046.
As your PLL frequency is very very low, you will face a lot of
difficulties due to leakage and other non-idealities of the
various components. I would recommend to use a digital PLL
implemented in a uC (PIC, AVR32, ARM Cortex-M0/M3) instead.
If you clock the uC from the 1MHz signal and use the
capture/compare (aka timer) unit of the uC will give you
a resolution in the region of 10-40ns, which should be good
enough considering the noise/stability of the pendulum.
With that you can easily implement a PLL with a loop time constant
of several seconds without the fear of running into problems from
the analog parts.
Attila Kinali
--
It is upon moral qualities that a society is ultimately founded. All
the prosperity and technological sophistication in the world is of no
use without that foundation.
-- Miss Matheson, The Diamond Age, Neil Stephenson
To get your loop to lock and keep phase noise down the loop filter would need a bandwidth of .05 Hz or less. That would mean long lock times. Very long lock times.
Engineering is the art of making what you want from what you can get at a profit.
I like Polywell Fusion.
On Tuesday, March 21, 2017 2:01 AM, David Scott Coburn <scotttt@optonline.net> wrote:
Hi All,
I have built and tested a PLL circuit that will be used to generate a 1 MHz signal locked to a 0.5 HZ signal from a pendulum. (Details available upon request.)
The circuit is a classic 4046 generating the 1 MHz signal which is fed into a 2e6 digital divider which outputs 0.5 Hz which is fed back to the 4046 phase comparator (PC).
I take a 1 MHz signal from an HP 107A run through another 2e6 divider to generate a reference 0.5 Hz signal for the other 4046 PC input.
I tested this by feeding the 0.5 Hz output of the PLL into a "time-stamp counter" board which I built to go into an HP 3582A Data Acquisition unit. The TSC uses the 5 MHz signal from the HP 107A to feed a free-running 32-bit binary counter. The 0.5 Hz input latches the count value (on the rising edge of the signal), which is then logged.
See the attached diagram. The PLL under test is in the red box. (Not sure what the policy is here for attachments?)
If all was perfect I would get a string of values of 10,000,000 counts each, one every 2 seconds.
Over the course of one day the average reading is, in fact, 10e6, so the PLL looks to be working over "long" time scales.
The attached histogram plot shows the actual data for the 0.5 Hz signal, showing the distribution of deviations from 10e6 counts. This is almost a full day of data, about 40,000 readings.
The standard deviation for the data is about 55 counts.
The plot looks to my eye to be a nice Gaussian shape, so I assume that the deviations are caused mainly by (white?) noise. There does not look to be much other structure in the shape of the data. (Comments welcome.)
Sorry for the long introduction, there are some questions coming!
I have looked for information on the web about others who may have done this kind of PLL, but did not find much.
Does anyone know of any articles related to this?
If so, do you know what kind of performance they got?
What kind of statement could I make about the 'stability' of this circuit? Simplistically: a 'stability' of ~50 counts in 10e6 is ~5e-7?
By the way, this performance is WAY WAY beyond what I was expecting....
Cheers,
Scott_______________________________________________
time-nuts mailing list -- time-nuts@febo.com
To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts
and follow the instructions there.
Hi Scott,
That's a nice project.
Combining quartz and pendulum like that is essentially how a GPSDO works. In your case, instead of a 10 MHz oscillator you have a 1 MHz oscillator and instead of 1PPS you have 1/2 PPS. Whether you use an analog loop or a digital loop there are dozens of examples on the web and hundreds of time-nuts postings that cover this territory.
Note that you have a choice of using the hp 107a quartz oscillator to discipline the pendulum, or use the pendulum to discipline the quartz. Each project has a certain charm.
Your decision to use a 32-bit time stamping counter (TSC) is good. Pendulum clocks tend to be less accurate than quartz oscillators and so they tend to "wrap" more often. A TSC avoids the zero boundary, sign, and sample rate issues that can plague a traditional start/stop, aka time interval counter (TIC).
A standard deviation of ~50 counts out to 10 million counts over a day represents a consistency or stability of 50 / 1e7 or 5e-6 or 5 ppm at "tau" 1 day. I would guess the shape of your Gaussian merely reflects the loop parameters you have chosen, and not so much the quality of the 1 MHz quartz or the 0.5 Hz pendulum. For example, tighten the loop and I bet your histogram will narrow.
I'm not sure of your terminology -- at one point you mention 1 MHz, then mention 10,000,000, then mention 10e6, which some people might read as 10^6 as in 1,000,000 or 1e6 and others may read as 10x10^6, as in 10^7 or 10,000,000 or 1e7.
Either way, this level of performance for a hp 107 oscillator or for a pendulum clock seems right. I don't think there's any problem with your setup. Pendulum clocks can easily get to ppm levels; some even get to ppb levels.
One suggestion is for you to make several runs against an independent reference: 1) hp 107A only, 2) pendulum only, 3) hp 107A and pendulum with PLL. When you see these ADEV plots you will get a hint of how the PLL should be tuned. Here's a classic example:
http://www.thinksrs.com/assets/instr/PRS10/PRS10diag2LG.gif
Some additional GPSDO, pendulum/PLL, pendulum ADEV links:
http://leapsecond.com/pages/gpsdo/
http://leapsecond.com/hsn2006/
/tvb
----- Original Message -----
From: "David Scott Coburn" scotttt@optonline.net
To: time-nuts@febo.com
Sent: Monday, March 20, 2017 6:07 PM
Subject: [time-nuts] PLL performance?
Hi All,
I have built and tested a PLL circuit that will be used to generate a 1 MHz signal locked to a 0.5 HZ signal from a pendulum. (Details available upon request.)
The circuit is a classic 4046 generating the 1 MHz signal which is fed into a 2e6 digital divider which outputs 0.5 Hz which is fed back to the 4046 phase comparator (PC).
I take a 1 MHz signal from an HP 107A run through another 2e6 divider to generate a reference 0.5 Hz signal for the other 4046 PC input.
I tested this by feeding the 0.5 Hz output of the PLL into a "time-stamp counter" board which I built to go into an HP 3582A Data Acquisition unit. The TSC uses the 5 MHz signal from the HP 107A to feed a free-running 32-bit binary counter. The 0.5 Hz input latches the count value (on the rising edge of the signal), which is then logged.
See the attached diagram. The PLL under test is in the red box. (Not sure what the policy is here for attachments?)
If all was perfect I would get a string of values of 10,000,000 counts each, one every 2 seconds.
Over the course of one day the average reading is, in fact, 10e6, so the PLL looks to be working over "long" time scales.
The attached histogram plot shows the actual data for the 0.5 Hz signal, showing the distribution of deviations from 10e6 counts. This is almost a full day of data, about 40,000 readings.
The standard deviation for the data is about 55 counts.
The plot looks to my eye to be a nice Gaussian shape, so I assume that the deviations are caused mainly by (white?) noise. There does not look to be much other structure in the shape of the data. (Comments welcome.)
Sorry for the long introduction, there are some questions coming!
I have looked for information on the web about others who may have done this kind of PLL, but did not find much.
Does anyone know of any articles related to this?
If so, do you know what kind of performance they got?
What kind of statement could I make about the 'stability' of this circuit? Simplistically: a 'stability' of ~50 counts in 10e6 is ~5e-7?
By the way, this performance is WAY WAY beyond what I was expecting....
Cheers,
Scott
Ack! Sorry for the questionable PDF file. It was generated by gnuplot on my Linux system.
I see that Tom has posted a gif of the image, so I won't duplicate it.
Cheers,
Scott
On Monday, March 20, 2017 10:36:05 PM EDT Bill Byrom wrote:
Hi, Scott. I rarely post here, but just noticed your post. I can open
the "PLL0.pdf" file, but the other files appears to be corrupted. Adobe
Acrobat Reader thinks it's not really a PDF file or it's corrupted. I'm
not ready to comment on the expected results yet, and would like to see
the histogram.
Are you using phase detector 1 or 2? What are the details for your loop
filter?
--
Bill Byrom N5BB
Thanks Tom.
Scott
On Tuesday, March 21, 2017 2:08:14 AM EDT Tom Van Baak wrote:
Andy, Bill, et al.
Attached is a GIF version of Scott's (unreadable?)
histogram-utcday21613x.pdf file.
/tvb
----- Original Message -----
From: "Andy" AI.egrps+tn@gmail.com
To: "Discussion of precise time and frequency measurement"
time-nuts@febo.com Sent: Tuesday, March 21, 2017 12:23 AM
Subject: Re: [time-nuts] PLL performance?
Second file successfully opened in Irfanview.
Three other PDF readers, including Adobe, could not open it.
Andy