Empathy List Archives

DS

David Scott Coburn

Wed, Mar 22, 2017 1:10 AM

On Tuesday, March 21, 2017 12:26:59 PM EDT Attila Kinali wrote:

Moin,

On Mon, 20 Mar 2017 21:07:03 -0400

David Scott Coburn scotttt@optonline.net wrote:

I have built and tested a PLL circuit that will be used to generate a 1
MHz
signal locked to a 0.5 HZ signal from a pendulum. (Details available upon
request.)

[...]

I tested this by feeding the 0.5 Hz output of the PLL into a "time-stamp
counter" board which I built to go into an HP 3582A Data Acquisition unit.

The TSC uses the 5 MHz signal from the HP 107A to feed a free-running
32-bit>
binary counter. The 0.5 Hz input latches the count value (on the rising
edge of the signal), which is then logged.

The VCO in the 4046 is an odd mixture between a relaxation and an
delay line oscillator. It's stability is not that good (at least
not by modern standards). As such, your phase comparator frequency
of just 0.5Hz is too low for the 4046 to show its peak performance,
as it is basically free running for 2s before a slight correction
is applied. Usually the frequencies used for a 4046 are in the range
of 1kHz to 100kHz.

Alternatively, you can dissable the internal VCO (inhibit pin) and
use an external oscillator that is more stable. The VCXOs by Abracon
(ASVTX-*) are readily available and cheap enough. If you use a 20MHz
oscillator (e.g. ASVTX-09-20) divide the output first by 2 (using a
D-flipflop) and then by 10 (e.g. using 74LV161)
until you are at 1Hz, then use second D-flipflops to get to 0.5Hz.
This gives you 1MHz inbetween.

I'll have a look at the ASVTX units. Thanks!

The standard deviation for the data is about 55 counts.

This means that your jitter (at 0.5Hz) is 11µs RMS.

The plot looks to my eye to be a nice Gaussian shape, so I assume that the
deviations are caused mainly by (white?) noise. There does not look to be
much other structure in the shape of the data. (Comments welcome.)

Yes, It looks very much Gauss shaped, it is very likely that this is
indeed a Gauss process, but to be sure (in a statistical sense) you
would need to do something like a qq-plot or similar to check,
whether it's actually a Gaus distribution (there are others that
look very similar). But for all practical purposes, that does not
really matter.

Please be aware that a noise process can be Gaussian and not be white.
E.g. 1/f-noise has a Gaussian distribution as well.

I have looked for information on the web about others who may have done
this kind of PLL, but did not find much.

Does anyone know of any articles related to this?

What information are you looking for?

I was curious if anyone else has tried to do a PLL with two 0.5 Hz signals.
Does not seem like a particularly popular pastime! I did find a few articles
which used a digital PLL to lock a OCXO to GPS at 1 Hz.

If so, do you know what kind of performance they got?

Your performance seem's ok, but limited by the VCO of the 4046.

It is OK, and better than I was expecting. It is probably good enough for its
intended purpose, but this being the time-nuts channel I will look into a
better VCO.

As your PLL frequency is very very low, you will face a lot of
difficulties due to leakage and other non-idealities of the
various components. I would recommend to use a digital PLL
implemented in a uC (PIC, AVR32, ARM Cortex-M0/M3) instead.
If you clock the uC from the 1MHz signal and use the
capture/compare (aka timer) unit of the uC will give you
a resolution in the region of 10-40ns, which should be good
enough considering the noise/stability of the pendulum.
With that you can easily implement a PLL with a loop time constant
of several seconds without the fear of running into problems from
the analog parts.

I was interested in doing this as an analog PLL, for the challenge. I've done
my time on microprocessors and microcontrollers!

			Attila Kinali

Cheers,

Scott

On Tuesday, March 21, 2017 12:26:59 PM EDT Attila Kinali wrote: > Moin, > > On Mon, 20 Mar 2017 21:07:03 -0400 > > David Scott Coburn <scotttt@optonline.net> wrote: > > I have built and tested a PLL circuit that will be used to generate a 1 > > MHz > > signal locked to a 0.5 HZ signal from a pendulum. (Details available upon > > request.) > > [...] > > > I tested this by feeding the 0.5 Hz output of the PLL into a "time-stamp > > counter" board which I built to go into an HP 3582A Data Acquisition unit. > > > > The TSC uses the 5 MHz signal from the HP 107A to feed a free-running > > 32-bit> > > binary counter. The 0.5 Hz input latches the count value (on the rising > > edge of the signal), which is then logged. > > The VCO in the 4046 is an odd mixture between a relaxation and an > delay line oscillator. It's stability is not that good (at least > not by modern standards). As such, your phase comparator frequency > of just 0.5Hz is too low for the 4046 to show its peak performance, > as it is basically free running for 2s before a slight correction > is applied. Usually the frequencies used for a 4046 are in the range > of 1kHz to 100kHz. > > Alternatively, you can dissable the internal VCO (inhibit pin) and > use an external oscillator that is more stable. The VCXOs by Abracon > (ASVTX-*) are readily available and cheap enough. If you use a 20MHz > oscillator (e.g. ASVTX-09-20) divide the output first by 2 (using a > D-flipflop) and then by 10 (e.g. using 74LV161) > until you are at 1Hz, then use second D-flipflops to get to 0.5Hz. > This gives you 1MHz inbetween. I'll have a look at the ASVTX units. Thanks! > > The standard deviation for the data is about 55 counts. > > This means that your jitter (at 0.5Hz) is 11µs RMS. > > > The plot looks to my eye to be a nice Gaussian shape, so I assume that the > > deviations are caused mainly by (white?) noise. There does not look to be > > much other structure in the shape of the data. (Comments welcome.) > > Yes, It looks very much Gauss shaped, it is very likely that this is > indeed a Gauss process, but to be sure (in a statistical sense) you > would need to do something like a qq-plot or similar to check, > whether it's actually a Gaus distribution (there are others that > look very similar). But for all practical purposes, that does not > really matter. > > Please be aware that a noise process can be Gaussian and not be white. > E.g. 1/f-noise has a Gaussian distribution as well. > > > I have looked for information on the web about others who may have done > > this kind of PLL, but did not find much. > > > > Does anyone know of any articles related to this? > > What information are you looking for? I was curious if anyone else has tried to do a PLL with two 0.5 Hz signals. Does not seem like a particularly popular pastime! I did find a few articles which used a digital PLL to lock a OCXO to GPS at 1 Hz. > > If so, do you know what kind of performance they got? > > Your performance seem's ok, but limited by the VCO of the 4046. It is OK, and better than I was expecting. It is probably good enough for its intended purpose, but this being the time-nuts channel I will look into a better VCO. > As your PLL frequency is very very low, you will face a lot of > difficulties due to leakage and other non-idealities of the > various components. I would recommend to use a digital PLL > implemented in a uC (PIC, AVR32, ARM Cortex-M0/M3) instead. > If you clock the uC from the 1MHz signal and use the > capture/compare (aka timer) unit of the uC will give you > a resolution in the region of 10-40ns, which should be good > enough considering the noise/stability of the pendulum. > With that you can easily implement a PLL with a loop time constant > of several seconds without the fear of running into problems from > the analog parts. I was interested in doing this as an analog PLL, for the challenge. I've done my time on microprocessors and microcontrollers! > > > Attila Kinali Cheers, Scott

DS

David Scott Coburn

Wed, Mar 22, 2017 1:26 AM

The loop filter does have a very low bandwidth, of the order you mentioned.

The lock time is surprisingly quick, but one man's pocket change may be another man's fortune....

I use a lag-lead filter with the PC2 comparator. It begins to 'track' after a minute or so.

From a cold start there is one large overshoot with the VCO frequency starting too low and then going high. On the scope you can then watch the VCO 0.5 Hz signal slowly sidle up to the reference 0.5 Hz signal over the course of a few more minutes.

It does take 10 or 15 minutes for it to settle to where the jitter is down into the 5th or 6th digit on my frequency counter though.

Scott

On Tuesday, March 21, 2017 12:14:15 PM EDT M. Simon via time-nuts wrote:up to

To get your loop to lock and keep phase noise down the loop filter would
need a bandwidth of .05 Hz or less. That would mean long lock times. Very
long lock times. Engineering is the art of making what you want from what
you can get at a profit. I like Polywell Fusion.

 On Tuesday, March 21, 2017 2:01 AM, David Scott Coburn

scotttt@optonline.net wrote:

<snip>

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https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the
instructions there.

The loop filter does have a very low bandwidth, of the order you mentioned. The lock time is surprisingly quick, but one man's pocket change may be another man's fortune.... I use a lag-lead filter with the PC2 comparator. It begins to 'track' after a minute or so. >From a cold start there is one large overshoot with the VCO frequency starting too low and then going high. On the scope you can then watch the VCO 0.5 Hz signal slowly sidle up to the reference 0.5 Hz signal over the course of a few more minutes. It does take 10 or 15 minutes for it to settle to where the jitter is down into the 5th or 6th digit on my frequency counter though. Scott On Tuesday, March 21, 2017 12:14:15 PM EDT M. Simon via time-nuts wrote:up to > To get your loop to lock and keep phase noise down the loop filter would > need a bandwidth of .05 Hz or less. That would mean long lock times. Very > long lock times. Engineering is the art of making what you want from what > you can get at a profit. I like Polywell Fusion. > > > On Tuesday, March 21, 2017 2:01 AM, David Scott Coburn > <scotttt@optonline.net> wrote: > <snip> > > > _______________________________________________ > time-nuts mailing list -- time-nuts@febo.com > To unsubscribe, go to > https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the > instructions there.

DS

David Scott Coburn

Wed, Mar 22, 2017 1:47 AM

On Tuesday, March 21, 2017 12:22:46 PM EDT Tom Van Baak wrote:

Hi Scott,

That's a nice project.

Combining quartz and pendulum like that is essentially how a GPSDO works. In
your case, instead of a 10 MHz oscillator you have a 1 MHz oscillator and
instead of 1PPS you have 1/2 PPS. Whether you use an analog loop or a
digital loop there are dozens of examples on the web and hundreds of
time-nuts postings that cover this territory.

I've looked for some, but did not find much. I guess I am not using the right search terms?

(Lots of PLL information on the web. Was having trouble finding others who had done this syncing of two 0.5 Hz, or similar, signals.)

Note that you have a choice of using the hp 107a quartz oscillator to
discipline the pendulum, or use the pendulum to discipline the quartz. Each
project has a certain charm.

This is part of a larger long-term project to build a precision dual pendulum set. The HP 107A will probably be involved in the instrumentation for monitoring the pendulums. (This is the subject of another posting later on.)

Your decision to use a 32-bit time stamping counter (TSC) is good. Pendulum
clocks tend to be less accurate than quartz oscillators and so they tend to
"wrap" more often. A TSC avoids the zero boundary, sign, and sample rate
issues that can plague a traditional start/stop, aka time interval counter
(TIC).

The TSC works very well.

A standard deviation of ~50 counts out to 10 million counts over a day
represents a consistency or stability of 50 / 1e7 or 5e-6 or 5 ppm at "tau"
1 day. I would guess the shape of your Gaussian merely reflects the loop
parameters you have chosen, and not so much the quality of the 1 MHz quartz
or the 0.5 Hz pendulum. For example, tighten the loop and I bet your
histogram will narrow.

I'm not sure of your terminology -- at one point you mention 1 MHz, then
mention 10,000,000, then mention 10e6, which some people might read as 10^6
as in 1,000,000 or 1e6 and others may read as 10x10^6, as in 10^7 or
10,000,000 or 1e7.

I guess this was a bit confusing. The 1 MHz is generated by the VCO. The 10,000,000 comes from counting the 5 MHz signal for 2 seconds. The 10e6 was intended to represent 10,000,000, but I see that would have been more clear as 10^7.

Either way, this level of performance for a hp 107 oscillator or for a
pendulum clock seems right. I don't think there's any problem with your
setup. Pendulum clocks can easily get to ppm levels; some even get to ppb
levels.

I was imagining that, to a first order, the stability of the HP 107A would not show up in the histogram to a noticeable degree over the course of the day. (If it drifts by 10^-12 during the day this would be only about 1/2 of a single 5 MHz cycle?)

I was assuming that for this purpose the HP 107A was 'perfect' and all of the jitter shown on the histogram is from the instability of the VCO.

One suggestion is for you to make several runs against an independent
reference: 1) hp 107A only, 2) pendulum only, 3) hp 107A and pendulum with
PLL. When you see these ADEV plots you will get a hint of how the PLL
should be tuned. Here's a classic example:

I don't have the pendulums yet! :)

I did run the setup with the PLL out of the loop. That is, just running the reference 0.5 Hz into the TSC. This gives me an endless stream of mildly uninteresting 10^7 readings...... (However, it does show that my TSC triggering and latching circuits are working correctly.)

http://www.thinksrs.com/assets/instr/PRS10/PRS10diag2LG.gif

Some additional GPSDO, pendulum/PLL, pendulum ADEV links:

http://leapsecond.com/pages/gpsdo/

http://leapsecond.com/hsn2006/

I hope to be generating plots like this some day.

/tvb

Cheers,

Scott

----- Original Message -----
From: "David Scott Coburn" scotttt@optonline.net
To: time-nuts@febo.com
Sent: Monday, March 20, 2017 6:07 PM
Subject: [time-nuts] PLL performance?

<snip>

time-nuts mailing list -- time-nuts@febo.com
To unsubscribe, go to
https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the
instructions there.

On Tuesday, March 21, 2017 12:22:46 PM EDT Tom Van Baak wrote: > Hi Scott, > > That's a nice project. > > Combining quartz and pendulum like that is essentially how a GPSDO works. In > your case, instead of a 10 MHz oscillator you have a 1 MHz oscillator and > instead of 1PPS you have 1/2 PPS. Whether you use an analog loop or a > digital loop there are dozens of examples on the web and hundreds of > time-nuts postings that cover this territory. I've looked for some, but did not find much. I guess I am not using the right search terms? (Lots of PLL information on the web. Was having trouble finding others who had done this syncing of two 0.5 Hz, or similar, signals.) > Note that you have a choice of using the hp 107a quartz oscillator to > discipline the pendulum, or use the pendulum to discipline the quartz. Each > project has a certain charm. This is part of a larger long-term project to build a precision dual pendulum set. The HP 107A will probably be involved in the instrumentation for monitoring the pendulums. (This is the subject of another posting later on.) > Your decision to use a 32-bit time stamping counter (TSC) is good. Pendulum > clocks tend to be less accurate than quartz oscillators and so they tend to > "wrap" more often. A TSC avoids the zero boundary, sign, and sample rate > issues that can plague a traditional start/stop, aka time interval counter > (TIC). The TSC works very well. > A standard deviation of ~50 counts out to 10 million counts over a day > represents a consistency or stability of 50 / 1e7 or 5e-6 or 5 ppm at "tau" > 1 day. I would guess the shape of your Gaussian merely reflects the loop > parameters you have chosen, and not so much the quality of the 1 MHz quartz > or the 0.5 Hz pendulum. For example, tighten the loop and I bet your > histogram will narrow. > > I'm not sure of your terminology -- at one point you mention 1 MHz, then > mention 10,000,000, then mention 10e6, which some people might read as 10^6 > as in 1,000,000 or 1e6 and others may read as 10x10^6, as in 10^7 or > 10,000,000 or 1e7. I guess this was a bit confusing. The 1 MHz is generated by the VCO. The 10,000,000 comes from counting the 5 MHz signal for 2 seconds. The 10e6 was intended to represent 10,000,000, but I see that would have been more clear as 10^7. > Either way, this level of performance for a hp 107 oscillator or for a > pendulum clock seems right. I don't think there's any problem with your > setup. Pendulum clocks can easily get to ppm levels; some even get to ppb > levels. I was imagining that, to a first order, the stability of the HP 107A would not show up in the histogram to a noticeable degree over the course of the day. (If it drifts by 10^-12 during the day this would be only about 1/2 of a single 5 MHz cycle?) I was assuming that for this purpose the HP 107A was 'perfect' and all of the jitter shown on the histogram is from the instability of the VCO. > One suggestion is for you to make several runs against an independent > reference: 1) hp 107A only, 2) pendulum only, 3) hp 107A and pendulum with > PLL. When you see these ADEV plots you will get a hint of how the PLL > should be tuned. Here's a classic example: I don't have the pendulums yet! :) I did run the setup with the PLL out of the loop. That is, just running the reference 0.5 Hz into the TSC. This gives me an endless stream of mildly uninteresting 10^7 readings...... (However, it does show that my TSC triggering and latching circuits are working correctly.) > > http://www.thinksrs.com/assets/instr/PRS10/PRS10diag2LG.gif > > Some additional GPSDO, pendulum/PLL, pendulum ADEV links: > > http://leapsecond.com/pages/gpsdo/ > > http://leapsecond.com/hsn2006/ I hope to be generating plots like this some day. > > /tvb Cheers, Scott > ----- Original Message ----- > From: "David Scott Coburn" <scotttt@optonline.net> > To: <time-nuts@febo.com> > Sent: Monday, March 20, 2017 6:07 PM > Subject: [time-nuts] PLL performance? > <snip> > > _______________________________________________ > time-nuts mailing list -- time-nuts@febo.com > To unsubscribe, go to > https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the > instructions there.

AK

Attila Kinali

Wed, Mar 22, 2017 11:54 AM

On Tue, 21 Mar 2017 21:10:19 -0400
David Scott Coburn scotttt@optonline.net wrote:

What information are you looking for?

I was curious if anyone else has tried to do a PLL with two 0.5 Hz signals.
Does not seem like a particularly popular pastime! I did find a few articles
which used a digital PLL to lock a OCXO to GPS at 1 Hz.

[...]

I was interested in doing this as an analog PLL, for the challenge. I've done
my time on microprocessors and microcontrollers!

There have been a couple of discussions about doing GPSDOs using only analog
components in the past. People fare more knowledgable than me have commented
there on what the challenges would be and how to solve them. So I recommend
to go through the archives and look for those discussions. They might be a
little bit hidden, though.

		Attila Kinali

--
It is upon moral qualities that a society is ultimately founded. All
the prosperity and technological sophistication in the world is of no
use without that foundation.
-- Miss Matheson, The Diamond Age, Neil Stephenson

On Tue, 21 Mar 2017 21:10:19 -0400 David Scott Coburn <scotttt@optonline.net> wrote: > > What information are you looking for? > > I was curious if anyone else has tried to do a PLL with two 0.5 Hz signals. > Does not seem like a particularly popular pastime! I did find a few articles > which used a digital PLL to lock a OCXO to GPS at 1 Hz. [...] > I was interested in doing this as an analog PLL, for the challenge. I've done > my time on microprocessors and microcontrollers! There have been a couple of discussions about doing GPSDOs using only analog components in the past. People fare more knowledgable than me have commented there on what the challenges would be and how to solve them. So I recommend to go through the archives and look for those discussions. They might be a little bit hidden, though. Attila Kinali -- It is upon moral qualities that a society is ultimately founded. All the prosperity and technological sophistication in the world is of no use without that foundation. -- Miss Matheson, The Diamond Age, Neil Stephenson

SS

Scott Stobbe

Wed, Mar 22, 2017 4:19 PM

Neat Project. I don't know if it will come up for you but optical or hall
rotary encoders are notorious for jitter. While a generic IC comparator may
have an open loop-gain of 100 dB, creating the mechanical equivalent is not
so easy. Hall/optical have a softer switch on/off curve. Depending what you
choose to instrument your pendulum may also introduce more jitter. The
20logN dosen't help either, 1 millideg at 0.5 Hz is 5.5 cycles at 1 MHz.

On Mon, Mar 20, 2017 at 9:07 PM, David Scott Coburn scotttt@optonline.net
wrote:

Hi All,

I have built and tested a PLL circuit that will be used to generate a 1
MHz signal locked to a 0.5 HZ signal from a pendulum. (Details available
upon request.)

The circuit is a classic 4046 generating the 1 MHz signal which is fed
into a 2e6 digital divider which outputs 0.5 Hz which is fed back to the
4046 phase comparator (PC).

I take a 1 MHz signal from an HP 107A run through another 2e6 divider to
generate a reference 0.5 Hz signal for the other 4046 PC input.

I tested this by feeding the 0.5 Hz output of the PLL into a "time-stamp
counter" board which I built to go into an HP 3582A Data Acquisition unit.
The TSC uses the 5 MHz signal from the HP 107A to feed a free-running
32-bit binary counter. The 0.5 Hz input latches the count value (on the
rising edge of the signal), which is then logged.

See the attached diagram. The PLL under test is in the red box. (Not
sure what the policy is here for attachments?)

If all was perfect I would get a string of values of 10,000,000 counts
each, one every 2 seconds.

Over the course of one day the average reading is, in fact, 10e6, so the
PLL looks to be working over "long" time scales.

The attached histogram plot shows the actual data for the 0.5 Hz signal,
showing the distribution of deviations from 10e6 counts. This is almost a
full day of data, about 40,000 readings.

The standard deviation for the data is about 55 counts.

The plot looks to my eye to be a nice Gaussian shape, so I assume that the
deviations are caused mainly by (white?) noise. There does not look to be
much other structure in the shape of the data. (Comments welcome.)

Sorry for the long introduction, there are some questions coming!

I have looked for information on the web about others who may have done
this kind of PLL, but did not find much.

Does anyone know of any articles related to this?

If so, do you know what kind of performance they got?

What kind of statement could I make about the 'stability' of this
circuit? Simplistically: a 'stability' of ~50 counts in 10e6 is ~5e-7?

By the way, this performance is WAY WAY beyond what I was expecting....

Cheers,

Scott

time-nuts mailing list -- time-nuts@febo.com
To unsubscribe, go to https://www.febo.com/cgi-bin/
mailman/listinfo/time-nuts
and follow the instructions there.

Neat Project. I don't know if it will come up for you but optical or hall rotary encoders are notorious for jitter. While a generic IC comparator may have an open loop-gain of 100 dB, creating the mechanical equivalent is not so easy. Hall/optical have a softer switch on/off curve. Depending what you choose to instrument your pendulum may also introduce more jitter. The 20logN dosen't help either, 1 millideg at 0.5 Hz is 5.5 cycles at 1 MHz. On Mon, Mar 20, 2017 at 9:07 PM, David Scott Coburn <scotttt@optonline.net> wrote: > Hi All, > > I have built and tested a PLL circuit that will be used to generate a 1 > MHz signal locked to a 0.5 HZ signal from a pendulum. (Details available > upon request.) > > The circuit is a classic 4046 generating the 1 MHz signal which is fed > into a 2e6 digital divider which outputs 0.5 Hz which is fed back to the > 4046 phase comparator (PC). > > I take a 1 MHz signal from an HP 107A run through another 2e6 divider to > generate a reference 0.5 Hz signal for the other 4046 PC input. > > I tested this by feeding the 0.5 Hz output of the PLL into a "time-stamp > counter" board which I built to go into an HP 3582A Data Acquisition unit. > The TSC uses the 5 MHz signal from the HP 107A to feed a free-running > 32-bit binary counter. The 0.5 Hz input latches the count value (on the > rising edge of the signal), which is then logged. > > See the attached diagram. The PLL under test is in the red box. (Not > sure what the policy is here for attachments?) > > If all was perfect I would get a string of values of 10,000,000 counts > each, one every 2 seconds. > > Over the course of one day the average reading is, in fact, 10e6, so the > PLL looks to be working over "long" time scales. > > The attached histogram plot shows the actual data for the 0.5 Hz signal, > showing the distribution of deviations from 10e6 counts. This is almost a > full day of data, about 40,000 readings. > > The standard deviation for the data is about 55 counts. > > The plot looks to my eye to be a nice Gaussian shape, so I assume that the > deviations are caused mainly by (white?) noise. There does not look to be > much other structure in the shape of the data. (Comments welcome.) > > Sorry for the long introduction, there are some questions coming! > > I have looked for information on the web about others who may have done > this kind of PLL, but did not find much. > > Does anyone know of any articles related to this? > > If so, do you know what kind of performance they got? > > What kind of statement could I make about the 'stability' of this > circuit? Simplistically: a 'stability' of ~50 counts in 10e6 is ~5e-7? > > By the way, this performance is WAY WAY beyond what I was expecting.... > > Cheers, > > Scott > _______________________________________________ > time-nuts mailing list -- time-nuts@febo.com > To unsubscribe, go to https://www.febo.com/cgi-bin/ > mailman/listinfo/time-nuts > and follow the instructions there. >

DS

David Scott Coburn

Wed, Mar 22, 2017 11:48 PM

I will not be using an off-the-shelf optical interrupter type sensor for this.

I have designed a custom IR LED -> IR photodiode unit which will have a flag that blocks half of the IR signal when the pendulum is stopped, and the motion of the pendulum will modulate this 50% signal from about 25% to 75%. The output will be an analog 'sine' wave. This sine wave goes into some custom analog electronics which separates the DC and AC parts of the signal, does some amplification, and then into a precision zero-crossing detector (ZCD) circuit. I have assembled these circuits and have been testing them at zero DC (ie, no DC offset or sine input). The next step is to connect the LED/photodiode circuit and characterize the circuit with just the DC signal (as it would be if the pendulum was not moving). This stage of the testing is looking for noise and long-term stability issues. I have not yet injected a reference sine signal to characterize the circuit's AC performance. On my todo list! :)

I hoped to characterize the jitter of the ZCD circuit with a good low-jitter reference AC signal as an input, but it is not trivial to generate such a signal! (Short of spending lots of $$$ on a good signal generator.) I have an HP3325A which I intend to use for this but the 0.5 Hz output has quite a lot of jitter (not unexpected considering the way it is generated). But, I guess this is not so much of an issue, since I just need to see if the ZCD circuit makes the jitter worse.

The PLL circuit will not be used to characterize the performance of the pendulum, it will just be used to drive the display. The output of the ZCD circuit will be fed directly into a 'time-stamp counter' circuit to monitor the pendulum performance. To some degree it will be good to have a nice low-jitter signal from the pendulum, but I am more interested in the longer-term performance , where the jitter (hopefully!) is all averaged out.

(The DC part of the signal will be monitored for changes in the LED output (to monitor its stability) and there is a precision rectifier circuit to monitor the amplitude of the AC part of the signal (which is proportional to the amplitude of the pendulum motion). And, there is a precision voltage reference for driving all of these circuits.)

Cheers,

Scott

(Maybe this answer was more than you bargained for!)

On Wednesday, March 22, 2017 12:19:09 PM EDT Scott Stobbe wrote:

Neat Project. I don't know if it will come up for you but optical or hall
rotary encoders are notorious for jitter. While a generic IC comparator may
have an open loop-gain of 100 dB, creating the mechanical equivalent is not
so easy. Hall/optical have a softer switch on/off curve. Depending what you
choose to instrument your pendulum may also introduce more jitter. The
20logN dosen't help either, 1 millideg at 0.5 Hz is 5.5 cycles at 1 MHz.

On Mon, Mar 20, 2017 at 9:07 PM, David Scott Coburn scotttt@optonline.net

wrote:

Hi All,

I have built and tested a PLL circuit that will be used to generate a 1
MHz signal locked to a 0.5 HZ signal from a pendulum. (Details available
upon request.)

<snip>

Cheers,

Scott

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I will not be using an off-the-shelf optical interrupter type sensor for this. I have designed a custom IR LED -> IR photodiode unit which will have a flag that blocks half of the IR signal when the pendulum is stopped, and the motion of the pendulum will modulate this 50% signal from about 25% to 75%. The output will be an analog 'sine' wave. This sine wave goes into some custom analog electronics which separates the DC and AC parts of the signal, does some amplification, and then into a precision zero-crossing detector (ZCD) circuit. I have assembled these circuits and have been testing them at zero DC (ie, no DC offset or sine input). The next step is to connect the LED/photodiode circuit and characterize the circuit with just the DC signal (as it would be if the pendulum was not moving). This stage of the testing is looking for noise and long-term stability issues. I have not yet injected a reference sine signal to characterize the circuit's AC performance. On my todo list! :) I hoped to characterize the jitter of the ZCD circuit with a good low-jitter reference AC signal as an input, but it is not trivial to generate such a signal! (Short of spending lots of $$$ on a *good* signal generator.) I have an HP3325A which I intend to use for this but the 0.5 Hz output has quite a lot of jitter (not unexpected considering the way it is generated). But, I guess this is not so much of an issue, since I just need to see if the ZCD circuit makes the jitter worse. The PLL circuit will not be used to characterize the performance of the pendulum, it will just be used to drive the display. The output of the ZCD circuit will be fed directly into a 'time-stamp counter' circuit to monitor the pendulum performance. To some degree it will be good to have a nice low-jitter signal from the pendulum, but I am more interested in the longer-term performance , where the jitter (hopefully!) is all averaged out. (The DC part of the signal will be monitored for changes in the LED output (to monitor its stability) and there is a precision rectifier circuit to monitor the amplitude of the AC part of the signal (which is proportional to the amplitude of the pendulum motion). And, there is a precision voltage reference for driving all of these circuits.) Cheers, Scott (Maybe this answer was more than you bargained for!) On Wednesday, March 22, 2017 12:19:09 PM EDT Scott Stobbe wrote: > Neat Project. I don't know if it will come up for you but optical or hall > rotary encoders are notorious for jitter. While a generic IC comparator may > have an open loop-gain of 100 dB, creating the mechanical equivalent is not > so easy. Hall/optical have a softer switch on/off curve. Depending what you > choose to instrument your pendulum may also introduce more jitter. The > 20logN dosen't help either, 1 millideg at 0.5 Hz is 5.5 cycles at 1 MHz. > > On Mon, Mar 20, 2017 at 9:07 PM, David Scott Coburn <scotttt@optonline.net> > > wrote: > > Hi All, > > > > I have built and tested a PLL circuit that will be used to generate a 1 > > MHz signal locked to a 0.5 HZ signal from a pendulum. (Details available > > upon request.) <snip> > > Cheers, > > > > Scott > > _______________________________________________ > > time-nuts mailing list -- time-nuts@febo.com > > To unsubscribe, go to https://www.febo.com/cgi-bin/ > > mailman/listinfo/time-nuts > > and follow the instructions there. > > _______________________________________________ > time-nuts mailing list -- time-nuts@febo.com > To unsubscribe, go to > https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the > instructions there.

PS

paul swed

Thu, Mar 23, 2017 3:34 PM

Hello to the group quite late to the discussion. Pretty interesting.
But I assume the drive for the pendulum is some impulse. Not the old
mechanical clock with a spring for power.
Regards
Paul
WB8TSL

On Wed, Mar 22, 2017 at 7:48 PM, David Scott Coburn scotttt@optonline.net
wrote:

I will not be using an off-the-shelf optical interrupter type sensor for
this.

I have designed a custom IR LED -> IR photodiode unit which will have a
flag that blocks half of the IR signal when the pendulum is stopped, and
the motion of the pendulum will modulate this 50% signal from about 25% to
75%. The output will be an analog 'sine' wave. This sine wave goes into
some custom analog electronics which separates the DC and AC parts of the
signal, does some amplification, and then into a precision zero-crossing
detector (ZCD) circuit. I have assembled these circuits and have been
testing them at zero DC (ie, no DC offset or sine input). The next step is
to connect the LED/photodiode circuit and characterize the circuit with
just the DC signal (as it would be if the pendulum was not moving). This
stage of the testing is looking for noise and long-term stability issues.
I have not yet injected a reference sine signal to characterize the
circuit's AC performance. On my todo list! :)

I hoped to characterize the jitter of the ZCD circuit with a good
low-jitter reference AC signal as an input, but it is not trivial to
generate such a signal! (Short of spending lots of $$$ on a good signal
generator.) I have an HP3325A which I intend to use for this but the 0.5
Hz output has quite a lot of jitter (not unexpected considering the way it
is generated). But, I guess this is not so much of an issue, since I just
need to see if the ZCD circuit makes the jitter worse.

The PLL circuit will not be used to characterize the performance of the
pendulum, it will just be used to drive the display. The output of the ZCD
circuit will be fed directly into a 'time-stamp counter' circuit to monitor
the pendulum performance. To some degree it will be good to have a nice
low-jitter signal from the pendulum, but I am more interested in the
longer-term performance , where the jitter (hopefully!) is all averaged out.

(The DC part of the signal will be monitored for changes in the LED output
(to monitor its stability) and there is a precision rectifier circuit to
monitor the amplitude of the AC part of the signal (which is proportional
to the amplitude of the pendulum motion). And, there is a precision
voltage reference for driving all of these circuits.)

Cheers,

Scott

(Maybe this answer was more than you bargained for!)

On Wednesday, March 22, 2017 12:19:09 PM EDT Scott Stobbe wrote:

Neat Project. I don't know if it will come up for you but optical or hall
rotary encoders are notorious for jitter. While a generic IC comparator

may

have an open loop-gain of 100 dB, creating the mechanical equivalent is

not

so easy. Hall/optical have a softer switch on/off curve. Depending what

you

choose to instrument your pendulum may also introduce more jitter. The
20logN dosen't help either, 1 millideg at 0.5 Hz is 5.5 cycles at 1 MHz.

On Mon, Mar 20, 2017 at 9:07 PM, David Scott Coburn <

scotttt@optonline.net>

wrote:

Hi All,

I have built and tested a PLL circuit that will be used to generate a 1
MHz signal locked to a 0.5 HZ signal from a pendulum. (Details

available

upon request.)

<snip>

Cheers,

Scott

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Hello to the group quite late to the discussion. Pretty interesting. But I assume the drive for the pendulum is some impulse. Not the old mechanical clock with a spring for power. Regards Paul WB8TSL On Wed, Mar 22, 2017 at 7:48 PM, David Scott Coburn <scotttt@optonline.net> wrote: > I will not be using an off-the-shelf optical interrupter type sensor for > this. > > I have designed a custom IR LED -> IR photodiode unit which will have a > flag that blocks half of the IR signal when the pendulum is stopped, and > the motion of the pendulum will modulate this 50% signal from about 25% to > 75%. The output will be an analog 'sine' wave. This sine wave goes into > some custom analog electronics which separates the DC and AC parts of the > signal, does some amplification, and then into a precision zero-crossing > detector (ZCD) circuit. I have assembled these circuits and have been > testing them at zero DC (ie, no DC offset or sine input). The next step is > to connect the LED/photodiode circuit and characterize the circuit with > just the DC signal (as it would be if the pendulum was not moving). This > stage of the testing is looking for noise and long-term stability issues. > I have not yet injected a reference sine signal to characterize the > circuit's AC performance. On my todo list! :) > > I hoped to characterize the jitter of the ZCD circuit with a good > low-jitter reference AC signal as an input, but it is not trivial to > generate such a signal! (Short of spending lots of $$$ on a *good* signal > generator.) I have an HP3325A which I intend to use for this but the 0.5 > Hz output has quite a lot of jitter (not unexpected considering the way it > is generated). But, I guess this is not so much of an issue, since I just > need to see if the ZCD circuit makes the jitter worse. > > The PLL circuit will not be used to characterize the performance of the > pendulum, it will just be used to drive the display. The output of the ZCD > circuit will be fed directly into a 'time-stamp counter' circuit to monitor > the pendulum performance. To some degree it will be good to have a nice > low-jitter signal from the pendulum, but I am more interested in the > longer-term performance , where the jitter (hopefully!) is all averaged out. > > (The DC part of the signal will be monitored for changes in the LED output > (to monitor its stability) and there is a precision rectifier circuit to > monitor the amplitude of the AC part of the signal (which is proportional > to the amplitude of the pendulum motion). And, there is a precision > voltage reference for driving all of these circuits.) > > Cheers, > > Scott > > (Maybe this answer was more than you bargained for!) > > On Wednesday, March 22, 2017 12:19:09 PM EDT Scott Stobbe wrote: > > Neat Project. I don't know if it will come up for you but optical or hall > > rotary encoders are notorious for jitter. While a generic IC comparator > may > > have an open loop-gain of 100 dB, creating the mechanical equivalent is > not > > so easy. Hall/optical have a softer switch on/off curve. Depending what > you > > choose to instrument your pendulum may also introduce more jitter. The > > 20logN dosen't help either, 1 millideg at 0.5 Hz is 5.5 cycles at 1 MHz. > > > > On Mon, Mar 20, 2017 at 9:07 PM, David Scott Coburn < > scotttt@optonline.net> > > > > wrote: > > > Hi All, > > > > > > I have built and tested a PLL circuit that will be used to generate a 1 > > > MHz signal locked to a 0.5 HZ signal from a pendulum. (Details > available > > > upon request.) > > <snip> > > > > Cheers, > > > > > > Scott > > > _______________________________________________ > > > time-nuts mailing list -- time-nuts@febo.com > > > To unsubscribe, go to https://www.febo.com/cgi-bin/ > > > mailman/listinfo/time-nuts > > > and follow the instructions there. > > > > _______________________________________________ > > time-nuts mailing list -- time-nuts@febo.com > > To unsubscribe, go to > > https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the > > instructions there. > > > _______________________________________________ > time-nuts mailing list -- time-nuts@febo.com > To unsubscribe, go to https://www.febo.com/cgi-bin/ > mailman/listinfo/time-nuts > and follow the instructions there. >

DS

David Scott Coburn

Thu, Mar 23, 2017 11:21 PM

Yes, this is not a spring powered clock with gears.

The pendulum will be impulsed every N swings by a small weight. (Not yet sure what N will be.)

Scott

On Thursday, March 23, 2017 11:34:44 AM EDT paul swed wrote:

Hello to the group quite late to the discussion. Pretty interesting.
But I assume the drive for the pendulum is some impulse. Not the old
mechanical clock with a spring for power.
Regards
Paul
WB8TSL

On Wed, Mar 22, 2017 at 7:48 PM, David Scott Coburn scotttt@optonline.net

wrote:

I will not be using an off-the-shelf optical interrupter type sensor for
this.

<snip>

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Yes, this is not a spring powered clock with gears. The pendulum will be impulsed every N swings by a small weight. (Not yet sure what N will be.) Scott On Thursday, March 23, 2017 11:34:44 AM EDT paul swed wrote: > Hello to the group quite late to the discussion. Pretty interesting. > But I assume the drive for the pendulum is some impulse. Not the old > mechanical clock with a spring for power. > Regards > Paul > WB8TSL > > On Wed, Mar 22, 2017 at 7:48 PM, David Scott Coburn <scotttt@optonline.net> > > wrote: > > I will not be using an off-the-shelf optical interrupter type sensor for > > this. > > <snip> > > _______________________________________________ > time-nuts mailing list -- time-nuts@febo.com > To unsubscribe, go to > https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the > instructions there.

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PLL performance?