Re: +1/f of transistors
On Samstag, 9. April 2022 13:38:58 CEST usenet@teply.info wrote:
IF the base and emitter doping would be done through ion implantation,
this can create a lot of defects, which act as recombination centres.
…as does any other doping technique. The details of what defects are where
and whether any of them are electrically active (beyond what constitutes the
activated dopants, i.e. the very much wanted part of doing it in the first
place) and if so how exactly is an interesting problem in itself to figure
out.
To the best of my knowledge, no hypothesis about the causal relationships of
these defects to 1/f noise is predictive beyond the often observed correlation
between having more of them without changing anything else (which really isn't
possible to do either) produces worse noise.
[…]
That's also a reason space guys often
require sourcing parts manufactured in one named fabrication plant.
I can't blame them. If you've ever been near a qualification where risk of 9+
figure budgets or limb&life is involved, then you too would probably come to
the conclusion very quickly that just the additional effort for qualifying a
second source when not necessary due to supply risk is something you need like
another hole in your head (even when everybody agrees that it should not add
any material risks).
Regards,
Achim.
+<[Q+ Matrix-12 WAVE#46+305 Neuron microQkb Andromeda XTk Blofeld]>+
Waldorf MIDI Implementation & additional documentation:
http://Synth.Stromeko.net/Downloads.html#WaldorfDocs
On 10.04.22 04:47, ghf@hoffmann-hochfrequenz.de wrote:
Am 2022-04-09 20:35, schrieb Lux, Jim:
On 4/9/22 10:03 AM, usenet@teply.info wrote:
On 09.04.22 15:31, Richard (Rick) Karlquist wrote:
I am seeing a lot of unsupported "theories" about what should be
done to make devices with low 1/f noise. It might be instructive
for everyone
to read Marv Keshner's PhD dissertation (Stanford) discussing 1/f
noise.
He looks at all kinds of theories and shows that there is no valid
cookbook for how to make low 1/f noise devices. It's the classic
non reproducible process. I remember an FCS
talk many years ago that NIST guru Fred Walls gave with some theory
on how to get low 1/f noise. Unlike his other papers which were
well received (and rightly so), this one was rapidly debunked.
I felt bad for Fred, getting out too far over his skills.
Thanks for the hint towards the thesis, I'll ask our library to fetch
a copy.
Recently I was discussing some measurement results with my colleagues
as we're trying to come up with a low noise JFET which can
successfully be integrated into a SiGe BiCMOS process, and quite
often we're also struggling to identify why exactly variant A has
significantly lower noise than variant B, or why a new approach does
not improve noise the way it was expected.
So from a manufacturing process design point of view, achieving low
1/f noise indeed is closer to sheer dumb luck than the proverbial
"more art than science" suggest.
This is very, very true. Some manufacturers get very low noise or very
low leakage (or both), essentially by being "lucky". From what I've
been told, there's no good models, nor predictions - so people share
"lore" of "if you get these 2Nxxxx FETs from the mfr in England,
they're really good" until they aren't. There isn't enough market
for these, so I suspect research money to "solve the problem" isn't
available.
Buy a life time supply while they are available. One reel will probably do.
Unfortunately, that's not always an option. Sometimes you only learn
that Part A is exceptionally good only when it isn't anymore. One of our
customers got bitten by that, relying on parts which exceeded specs
until they got transferred to another fab. Afterwards, the part still
met their specs, but didn't meet the customers requirements. Of course
the manufacturer put in some effort trying to make the device as good as
it was because it was a good customer, but there's only so much effort
you can justify for 100k parts a year. For small-value varicaps, where
you can dice easily 30k-50k pieces out of a single wafer, the customer
would happily have bought a full manufacturing lot had they known before
the fact.
Like all those microwave MMICs with low noise, they worry about 100
MHz and up (if not 1GHz), they certainly don't worry (or control) for
noise at 5 MHz, or where the 1/f knee is. So just because you got good
results with a batch of them, the next batch might not. It's not even
clear you could come up with a standardized test method, because the
noise depends on a lot of other factors (drain current, for instance).
When it changes from lot to lot, then you have lost. You cannot catch
that on the wafer tester. No one can pay for the tester time.
A simple BJT or FET circuit is allotted a ms or so in total, maybe.
You cannot measure 1/f in the 100 Hz range in that time. The picture
of the FET amplifier I had 3 days ago took 35 minutes, per trace.
By far, most of the wall time is aquisition time for the lowest octaves.
It depends a bit on the needs. Whether we're talking about DC, analog,
RF or digital testers for example. But even for the most complex tests,
tester time is cheap compared to engineering time for test setup.
But of course you're right, as 1/f takes long, one will have to trade
test time versus lower frequency corner and sample count. Doing full
manufacturing screening (as in test every single manufactured device) is
prohibitively costly more or less independent of lower frequency corner
for all but the most demanding applications. Testing a dozen devices out
of a full wafer (with, say, 10 k devices per wafer) is manageable. Last
year I measured a few samples for 1/f down to 0.01 Hz. That's a matter
of starting the measurement on friday afternoon and then going home for
the weekend. Next sample on the next weekend ;-) There was no point in
starting the measurement before friday afternoon in any case as during
the week the environment was more noisy than the DUT...
Florian
Am 2022-04-10 18:09, schrieb usenet@teply.info:
On 10.04.22 04:47, ghf@hoffmann-hochfrequenz.de wrote:
Recently I was discussing some measurement results with my
colleagues as we're trying to come up with a low noise JFET which
can successfully be integrated into a SiGe BiCMOS process, and quite
often we're also struggling to identify why exactly variant A has
significantly lower noise than variant B, or why a new approach does
not improve noise the way it was expected.
So from a manufacturing process design point of view, achieving low
1/f noise indeed is closer to sheer dumb luck than the proverbial
"more art than science" suggest.
This is very, very true. Some manufacturers get very low noise or
very
low leakage (or both), essentially by being "lucky". From what I've
been told, there's no good models, nor predictions - so people share
"lore" of "if you get these 2Nxxxx FETs from the mfr in England,
they're really good" until they aren't. There isn't enough market
for these, so I suspect research money to "solve the problem" isn't
available.
Buy a life time supply while they are available. One reel will
probably do.
Unfortunately, that's not always an option. Sometimes you only learn
that Part A is exceptionally good only when it isn't anymore. One of
our customers got bitten by that, relying on parts which exceeded
specs until they got transferred to another fab. Afterwards, the part
still met their specs, but didn't meet the customers requirements. Of
course the manufacturer put in some effort trying to make the device
as good as it was because it was a good customer, but there's only so
much effort you can justify for 100k parts a year. For small-value
varicaps, where you can dice easily 30k-50k pieces out of a single
wafer, the customer would happily have bought a full manufacturing lot
had they known before the fact.
Like all those microwave MMICs with low noise, they worry about 100
MHz and up (if not 1GHz), they certainly don't worry (or control) for
noise at 5 MHz, or where the 1/f knee is. So just because you got
good
results with a batch of them, the next batch might not. It's not
even
clear you could come up with a standardized test method, because the
noise depends on a lot of other factors (drain current, for
instance).
When it changes from lot to lot, then you have lost. You cannot catch
that on the wafer tester. No one can pay for the tester time.
A simple BJT or FET circuit is allotted a ms or so in total, maybe.
You cannot measure 1/f in the 100 Hz range in that time. The picture
of the FET amplifier I had 3 days ago took 35 minutes, per trace.
By far, most of the wall time is aquisition time for the lowest
octaves.
It depends a bit on the needs. Whether we're talking about DC, analog,
RF or digital testers for example. But even for the most complex
tests, tester time is cheap compared to engineering time for test
setup.
I've worked for a tester manufacturer near Stuttgart for a project, and
their customers had a completely different view about this. :-)
I had a mid-scale mixed signal tester just for myself to exercise my
software; only half a day per week for someone else's regression tests.
In our hall there were 300 engineers, almost entirely for software, only
15 or so for hardware design. A different customer of mine was quite
proud on their E5052B; in the neighbor cubicle someone sent half a dozen
of them one morning to calibration. That did not create any bottleneck.
That all must be paid for. Then you arrive at options: Normal vector
speed is <crawl>. For $$$ you get 10eXYZZY vectors at warp speed. Once.
My VNA cannot handle mixers because of a missing software option. As
much
as I hate it, I can understand it.
But of course you're right, as 1/f takes long, one will have to trade
test time versus lower frequency corner and sample count. Doing full
manufacturing screening (as in test every single manufactured device)
is prohibitively costly more or less independent of lower frequency
corner for all but the most demanding applications. Testing a dozen
devices out of a full wafer (with, say, 10 k devices per wafer) is
manageable. Last year I measured a few samples for 1/f down to 0.01
Hz. That's a matter of starting the measurement on friday afternoon
and then going home for the weekend. Next sample on the next weekend
;-) There was no point in starting the measurement before friday
afternoon in any case as during the week the environment was more
noisy than the DUT...
Reminds me of our bit error rate measurements in fiber optics. We had
to make sure, that NOBODY, not even the CEO took his cell phone into the
lab.
Can you tell us what you used as bias and power supplies for these 0.01
Hz
measurements? A tiny hint? Please, pretty please?
In Art Of Electronics ed 3 of Hill & Horowitz is a transistor noise
measurement circuit. I have built it, but then featuritis crept in:
NPN, PNP, JFETS, enhancement & depletion, fat decoupling that must
be polarity-switched...
I still have problems / doubts with the bias supply, I must simplify
the entire thing. Maybe I'll make a board layout.
regards, Gerhard.
On 10.04.22 21:03, ghf@hoffmann-hochfrequenz.de wrote:
Am 2022-04-10 18:09, schrieb usenet@teply.info:
On 10.04.22 04:47, ghf@hoffmann-hochfrequenz.de wrote:
Recently I was discussing some measurement results with my
colleagues as we're trying to come up with a low noise JFET which
can successfully be integrated into a SiGe BiCMOS process, and
quite often we're also struggling to identify why exactly variant A
has significantly lower noise than variant B, or why a new approach
does not improve noise the way it was expected.
So from a manufacturing process design point of view, achieving low
1/f noise indeed is closer to sheer dumb luck than the proverbial
"more art than science" suggest.
This is very, very true. Some manufacturers get very low noise or very
low leakage (or both), essentially by being "lucky". From what I've
been told, there's no good models, nor predictions - so people share
"lore" of "if you get these 2Nxxxx FETs from the mfr in England,
they're really good" until they aren't. There isn't enough market
for these, so I suspect research money to "solve the problem" isn't
available.
Buy a life time supply while they are available. One reel will
probably do.
Unfortunately, that's not always an option. Sometimes you only learn
that Part A is exceptionally good only when it isn't anymore. One of
our customers got bitten by that, relying on parts which exceeded
specs until they got transferred to another fab. Afterwards, the part
still met their specs, but didn't meet the customers requirements. Of
course the manufacturer put in some effort trying to make the device
as good as it was because it was a good customer, but there's only so
much effort you can justify for 100k parts a year. For small-value
varicaps, where you can dice easily 30k-50k pieces out of a single
wafer, the customer would happily have bought a full manufacturing lot
had they known before the fact.
Like all those microwave MMICs with low noise, they worry about 100
MHz and up (if not 1GHz), they certainly don't worry (or control) for
noise at 5 MHz, or where the 1/f knee is. So just because you got good
results with a batch of them, the next batch might not. It's not even
clear you could come up with a standardized test method, because the
noise depends on a lot of other factors (drain current, for instance).
When it changes from lot to lot, then you have lost. You cannot catch
that on the wafer tester. No one can pay for the tester time.
A simple BJT or FET circuit is allotted a ms or so in total, maybe.
You cannot measure 1/f in the 100 Hz range in that time. The picture
of the FET amplifier I had 3 days ago took 35 minutes, per trace.
By far, most of the wall time is aquisition time for the lowest octaves.
It depends a bit on the needs. Whether we're talking about DC, analog,
RF or digital testers for example. But even for the most complex
tests, tester time is cheap compared to engineering time for test
setup.
I've worked for a tester manufacturer near Stuttgart for a project, and
their customers had a completely different view about this. :-)
I had a mid-scale mixed signal tester just for myself to exercise my
software; only half a day per week for someone else's regression tests.
In our hall there were 300 engineers, almost entirely for software, only
15 or so for hardware design. A different customer of mine was quite
proud on their E5052B; in the neighbor cubicle someone sent half a dozen
of them one morning to calibration. That did not create any bottleneck.
That all must be paid for. Then you arrive at options: Normal vector
speed is <crawl>. For $$$ you get 10eXYZZY vectors at warp speed. Once.
My VNA cannot handle mixers because of a missing software option. As much
as I hate it, I can understand it.
But of course you're right, as 1/f takes long, one will have to trade
test time versus lower frequency corner and sample count. Doing full
manufacturing screening (as in test every single manufactured device)
is prohibitively costly more or less independent of lower frequency
corner for all but the most demanding applications. Testing a dozen
devices out of a full wafer (with, say, 10 k devices per wafer) is
manageable. Last year I measured a few samples for 1/f down to 0.01
Hz. That's a matter of starting the measurement on friday afternoon
and then going home for the weekend. Next sample on the next weekend
;-) There was no point in starting the measurement before friday
afternoon in any case as during the week the environment was more
noisy than the DUT...
Reminds me of our bit error rate measurements in fiber optics. We had
to make sure, that NOBODY, not even the CEO took his cell phone into the
lab.
If it was only cellphones it would have been too easy. Shielding 900 and
1800 MHz is not really a problem. But removing the crud the MBE
downstairs leaves on the mains lines is something that I didn't manage
successfully yet. But on weekends there's nobody operating it 8-P
Can you tell us what you used as bias and power supplies for these 0.01 Hz
measurements? A tiny hint? Please, pretty please?
Sure I can. It's not much black magic involved after all in the parts I
know: For Collector Bias, I used a stack of rechargeable batteries and a
few relays to change voltage, plus a DMM (HP 34401A) to measure the
actual voltage and current. For the base, two of these had to do
together with another relay-switched resistive divider. That has been
provided by our customer along with the DUTs. I believe it was 2V
lead-acid batteries, as they were a tad heavy. On the last sample I also
tried one of our Agilent E5270B SMU Mainframes, and worked quite okay as
well as the DUTs were not as low noise as has been hoped. But with that
I only went down to 0.1 Hz due to time constraints. You have to keep in
mind however that the test system in use (Proplus 9812DX) also does some
filtering (unfortunately I can't give you details here as I don't know
exactly) on the supplies, which probably helped as well.
At least I'm not aware of situations where the E5270B actually posed a
limit here.
Bests,
Florian DH7FET
Reply split into two posts in order to better follow the flow of
discussion...
On 12.04.22 00:02, Joseph Gwinn wrote:
On 09.04.22 13:38, usenet@teply.info wrote:
On 07.04.22 22:58, Joseph Gwinn wrote:
Those SiGe transistors have wonderful low Rbb of just a few Ohms,
which results in nice low voltage noise, but some have 1/f corners
of 50 MHz or more; that kills my application completely.
While these chips are small, they are made from very clean material,
so one wonders why so high. The circuit should be physically designed
as if it were to be handling GHz signals, because it could be
oscillating far above the capability of available instruments to
detect.
IF the base and emitter doping would be done through ion implantation,
this can create a lot of defects, which act as recombination centres.
I always wondered about such details. I gather from this and some
following posts that it is known how to greatly reduce 1/f noise in
transistors, but it's a nuisance, and so isn't generally done. But
what saves us is if the intended purpose of the transistor type
requires the cleanest of material and the best processes to yield low
defects such as trapping centers. Such as the above-mentioned
difficulties in getting the in-situ doping correct in SiGe
transistors.
I wouldn't go as far as saying that we KNOW EXACTLY how to reduce 1/f
noise or all the other unwanted side effects (RTN, leakage currents, you
name it). We do observe however, that in many cases these effect are
somewhat correlated with each other and with a variety of defects.
In many cases, these defects can be annealed (mostly through high
temperatures), but there's you get into conflict with other physical
properties you want to achive. One example: for modern three-digit GHz
fT SiGe HBTs (and also for double-digit GHz devices...), you'll need a
very thin base and a sharp doping profile. Application of high
temperatures for extended periods not only anneals the defects, but also
enhances diffusion of the dopant atoms so the can move along their
concentration gradient. Such spreading of the doping profiles and
germanium contents however is detrimental to their RF performance, as a
wider base and/or less steep doping profiles correlate to lower fT and
fMAX.
Bests,
Florian
Second part of reply to Joseph Gwinn...
On 12.04.22 00:02, Joseph Gwinn wrote:
On 09.04.22 20:35, Lux, Jim wrote:
On 4/9/22 10:03 AM, usenet@teply.info wrote:
Recently I was discussing some measurement results with my colleagues
as we're trying to come up with a low noise JFET which can
successfully be integrated into a SiGe BiCMOS process, and quite often
we're also struggling to identify why exactly variant A has
significantly lower noise than variant B, or why a new approach does
not improve noise the way it was expected.
So from a manufacturing process design point of view, achieving low
1/f noise indeed is closer to sheer dumb luck than the proverbial
"more art than science" suggest.
This is very, very true. Some manufacturers get very low noise or very
low leakage (or both), essentially by being "lucky". From what I've
been told, there's no good models, nor predictions - so people share
"lore" of "if you get these 2Nxxxx FETs from the mfr in England, they're
really good" until they aren't. There isn't enough market for these,
so I suspect research money to "solve the problem" isn't available.
Like all those microwave MMICs with low noise, they worry about 100 MHz
and up (if not 1GHz), they certainly don't worry (or control) for noise
at 5 MHz, or where the 1/f knee is. So just because you got good results
with a batch of them, the next batch might not. It's not even clear you
could come up with a standardized test method, because the noise depends
on a lot of other factors (drain current, for instance).
I bet (hope?) it isn't quite that bad.
But the fact that one cannot test and sort for 10-Hz flicker noise in
three milliseconds would suffice.
My experience is probably not representative of the semiconductor
industry as a whole, especially as unlike the big players we run a mix
of different processes on our line and are also have to deal with nearly
no redundancy in equipment instead of industry practice which boils down
to running one single process only per line if possible and having
several identical lines run in parallel, so that tool downtime on one
line can at best be compensated by using tools of the other identical lines.
But in my experience it's not uncommon to find that subsequent lots of
one particular product vary significantly in various parameters. Of
course these "subsequent" lots usually do not run back-to-back, so they
have a random combination of lots of different processes between them,
which pretty likely is at least part of the problem, but even if we run
several lots back-to-back, they never come out identical. Variation is
somewhat reduced on back-to-back lots, but still easily observable even
in non-critical parameters (non-critical in the sense of not reacting
much to changes in conditions).
Even though we're measuring noise only if there's a specific request for
it, we do occasionally see significant variation of 1/f corner frequency
even between nominally identical devices on the same wafer. Clearly, if
devices vary within one single wafer, you shouldn't expect to do better
from lot to lot with who knows what happened in between in the
processing line. And if you see significant variation within one wafer,
you essentially have to measure a significant portion of the devices on
the wafer to be sure your device sampling is still representative of the
wafer as a whole so you can reliably determine whether or not a wafer
meets your spec, driving up your test time.
But to put things into perspective: We do spend about 2 to 3 hours of
testing time per wafer (only parametric testing of DC and RF, not
including functional testing of customer devices) in total with
approximately 20% of the dies measured. Spending one more minute per die
for 1/f noise assuming we can get away with the same sampling scheme
would be very much manageable.
Bests,
Florian