Sub-ps delay line
Hello,
I'm looking/designing a sub-ps delay line with very high stability.
Basically it has microwave requirements on phase matching.
The main features that such delay line should have are:
- sub-ps resolution and about 1 ns range
- High stability, must not drift more than 2ps/year, preferably 1ps/year
- Temperature coefficient (tempco) below 1 ps/celsius
- Low phase noise floor, target random jitter below 100 fs RSM from 100Hz
to 1MHz. - flicker noise below -90dBc at 1Hz (100MHz carrier)
- cheap (below 50 euros) and PCB integrable
- optional: autocalibration or a way to check calibration health over time
(checking the oscillation frequency of the delay line connected as loop?)
Operating conditions: The delay line will be used for RF distribution,
where the clock signals (100-200MHz) must stay in +/- 10 ps error window.
Since timing jitter (wander) is 1.6ps RMS, the delay line must be very
accurate, with maximum of +/- 3ps of delay uncertainty. The delay line is
used to phase-match the clock outputs at factory, hence will not be
anymore modified (or for only fine corrections, tens of picoseconds). The
factory calibration compensates for the delay line and PCB
process/production variations. The boards will operate at almost same
temperature and humidity levels over years of continuous running.
Circuit constrains: The delay line is fed with an AC-coupled LVPECL clock
output (only P output used) and should provides a single-ended AC clock
output signal.
Indeed, no commercial chip fits into these requirements.
My idea is to use an RC filter to delay the input clock signal and then to
restore the clock edges with a LTC6957-1 (LVPECL outputs).
The RC filter would be realized using a varactor (Skyworks SMVA1470-004LF)
and a 16-bit DAC to control the voltage bias (+ stable voltage reference).
I already checked the values, and sub-ps resolution seems easily
achievable. The solution requires a factory calibration due to the
non-linear behavior of the varactor, but since I only need small
adjustments, this is not a problem.
The problem is to guarantee the calibration over years of operation.
Since a femtofarad parasitic capacitance can change the delay, I already
thought about protecting the delay line with some kind of resin (Epoxy?)
and/or a RF cage to protect it from dirt and moisture.
One of the issue is aging. I derived a typical varactor aging from VCTCXO
oscillators (no varactor manufacturer knows the effects of aging on its
products, apparently) and it's still good. But the aging of LTC6957 is not
known.
Is the PCB fabrication using microwave requirements on the dielectric fine?
Based on your experience, do you think that such delay line can respect the
requirements listed above, especially stability?
Am I missing something?
Thank you!
cheers,
Mattia Rizzi
In message CADv+7GhU-TKUN0OwXF99THpoHnQVp_mgFyG5cZZA0FXbOuQWCg@mail.gmail.com
, Mattia Rizzi writes:
I'm looking/designing a sub-ps delay line with very high stability.
Basically it has microwave requirements on phase matching.
The main features that such delay line should have are:
- sub-ps resolution and about 1 ns range
Put a length of coax in an adjustable oven ?
--
Poul-Henning Kamp | UNIX since Zilog Zeus 3.20
phk@FreeBSD.ORG | TCP/IP since RFC 956
FreeBSD committer | BSD since 4.3-tahoe
Never attribute to malice what can adequately be explained by incompetence.
I would also advise you take a look at how well you can maintain your
system impedance, say 50 Ohms. For example, I have seen about 100's ps
phase difference on a 10 MHz reference, using one BNC female-female coupler
versus another, a small part is due to TOF, but most of that is due to
subtle differences in the impedance of each coupler, thus by causing
reflections. The same is true for one cable versus another.
On Tue, Feb 7, 2017 at 11:13 AM, Mattia Rizzi mattia.rizzi@gmail.com
wrote:
Hello,
I'm looking/designing a sub-ps delay line with very high stability.
Basically it has microwave requirements on phase matching.
The main features that such delay line should have are:
- sub-ps resolution and about 1 ns range
- High stability, must not drift more than 2ps/year, preferably 1ps/year
- Temperature coefficient (tempco) below 1 ps/celsius
- Low phase noise floor, target random jitter below 100 fs RSM from 100Hz
to 1MHz. - flicker noise below -90dBc at 1Hz (100MHz carrier)
- cheap (below 50 euros) and PCB integrable
- optional: autocalibration or a way to check calibration health over time
(checking the oscillation frequency of the delay line connected as loop?)
Operating conditions: The delay line will be used for RF distribution,
where the clock signals (100-200MHz) must stay in +/- 10 ps error window.
Since timing jitter (wander) is 1.6ps RMS, the delay line must be very
accurate, with maximum of +/- 3ps of delay uncertainty. The delay line is
used to phase-match the clock outputs at factory, hence will not be
anymore modified (or for only fine corrections, tens of picoseconds). The
factory calibration compensates for the delay line and PCB
process/production variations. The boards will operate at almost same
temperature and humidity levels over years of continuous running.
Circuit constrains: The delay line is fed with an AC-coupled LVPECL clock
output (only P output used) and should provides a single-ended AC clock
output signal.
Indeed, no commercial chip fits into these requirements.
My idea is to use an RC filter to delay the input clock signal and then to
restore the clock edges with a LTC6957-1 (LVPECL outputs).
The RC filter would be realized using a varactor (Skyworks SMVA1470-004LF)
and a 16-bit DAC to control the voltage bias (+ stable voltage reference).
I already checked the values, and sub-ps resolution seems easily
achievable. The solution requires a factory calibration due to the
non-linear behavior of the varactor, but since I only need small
adjustments, this is not a problem.
The problem is to guarantee the calibration over years of operation.
Since a femtofarad parasitic capacitance can change the delay, I already
thought about protecting the delay line with some kind of resin (Epoxy?)
and/or a RF cage to protect it from dirt and moisture.
One of the issue is aging. I derived a typical varactor aging from VCTCXO
oscillators (no varactor manufacturer knows the effects of aging on its
products, apparently) and it's still good. But the aging of LTC6957 is not
known.
Is the PCB fabrication using microwave requirements on the dielectric fine?
Based on your experience, do you think that such delay line can respect the
requirements listed above, especially stability?
Am I missing something?
Thank you!
cheers,
Mattia Rizzi
time-nuts mailing list -- time-nuts@febo.com
To unsubscribe, go to https://www.febo.com/cgi-bin/
mailman/listinfo/time-nuts
and follow the instructions there.
Hello,
Put a length of coax in an adjustable oven ?
Using the numbers provided by [1], RG58 has about -0.152 ps/m/deg. I need
1 ns range, cable length is prohibitive.
cheers,
Mattia
[1] http://www.hepl.hiroshima-u.ac.jp/phx/notes/cable/cable.html
2017-02-07 18:04 GMT+01:00 Poul-Henning Kamp phk@phk.freebsd.dk:
In message <CADv+7GhU-TKUN0OwXF99THpoHnQVp_mgFyG5cZZA0FXbOuQWCg@mail.
gmail.com>
, Mattia Rizzi writes:
I'm looking/designing a sub-ps delay line with very high stability.
Basically it has microwave requirements on phase matching.
The main features that such delay line should have are:
- sub-ps resolution and about 1 ns range
Put a length of coax in an adjustable oven ?
--
Poul-Henning Kamp | UNIX since Zilog Zeus 3.20
phk@FreeBSD.ORG | TCP/IP since RFC 956
FreeBSD committer | BSD since 4.3-tahoe
Never attribute to malice what can adequately be explained by incompetence.
Since you need a set-and-forget type of solution, could you use a wide trace on your board and laser etch/mill it to set your delay, similar to the way film resistors are trimmed? IOW, add length by turning the wide trace into a zig-zag.
Bob -----------------------------------------------------------------AE6RV.com
GFS GPSDO list:
groups.yahoo.com/neo/groups/GFS-GPSDOs/info
From: Mattia Rizzi <mattia.rizzi@gmail.com>
To: Discussion of precise time and frequency measurement time-nuts@febo.com
Sent: Tuesday, February 7, 2017 10:13 AM
Subject: [time-nuts] Sub-ps delay line
Hello,
I'm looking/designing a sub-ps delay line with very high stability.
Basically it has microwave requirements on phase matching.
The main features that such delay line should have are:
- sub-ps resolution and about 1 ns range
- High stability, must not drift more than 2ps/year, preferably 1ps/year
- Temperature coefficient (tempco) below 1 ps/celsius
- Low phase noise floor, target random jitter below 100 fs RSM from 100Hz
to 1MHz. - flicker noise below -90dBc at 1Hz (100MHz carrier)
- cheap (below 50 euros) and PCB integrable
- optional: autocalibration or a way to check calibration health over time
(checking the oscillation frequency of the delay line connected as loop?)
Operating conditions: The delay line will be used for RF distribution,
where the clock signals (100-200MHz) must stay in +/- 10 ps error window.
Since timing jitter (wander) is 1.6ps RMS, the delay line must be very
accurate, with maximum of +/- 3ps of delay uncertainty. The delay line is
used to phase-match the clock outputs at factory, hence will not be
anymore modified (or for only fine corrections, tens of picoseconds). The
factory calibration compensates for the delay line and PCB
process/production variations. The boards will operate at almost same
temperature and humidity levels over years of continuous running.
Circuit constrains: The delay line is fed with an AC-coupled LVPECL clock
output (only P output used) and should provides a single-ended AC clock
output signal.
Indeed, no commercial chip fits into these requirements.
My idea is to use an RC filter to delay the input clock signal and then to
restore the clock edges with a LTC6957-1 (LVPECL outputs).
The RC filter would be realized using a varactor (Skyworks SMVA1470-004LF)
and a 16-bit DAC to control the voltage bias (+ stable voltage reference).
I already checked the values, and sub-ps resolution seems easily
achievable. The solution requires a factory calibration due to the
non-linear behavior of the varactor, but since I only need small
adjustments, this is not a problem.
The problem is to guarantee the calibration over years of operation.
Since a femtofarad parasitic capacitance can change the delay, I already
thought about protecting the delay line with some kind of resin (Epoxy?)
and/or a RF cage to protect it from dirt and moisture.
One of the issue is aging. I derived a typical varactor aging from VCTCXO
oscillators (no varactor manufacturer knows the effects of aging on its
products, apparently) and it's still good. But the aging of LTC6957 is not
known.
Is the PCB fabrication using microwave requirements on the dielectric fine?
Based on your experience, do you think that such delay line can respect the
requirements listed above, especially stability?
Am I missing something?
Thank you!
cheers,
Mattia Rizzi
time-nuts mailing list -- time-nuts@febo.com
To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts
and follow the instructions there.
I did something similar a couple years ago to make an adjustable 75
nanosecond pretrigger for my sampling oscilloscope so I will just pass
along some things I learned.
Power supply noise will create jitter in single ended logic because of
lack of power supply rejection. Temperature will be a problem with
single ended logic also although I did not care about that. The delay
section certainly needs to be differential which the LTC6957-1 neatly
covers; I was planning to use a comparator or line receiver next time
but the LTC6957-1 looks ideal.
With the above in mind, I would use a separate reference quality
regulator for the supply voltages and any reference levels. I only
needed 10s of picosecond stability and picosecond level jitter but I
suspect at the level of precision you desire, ground loops need to be
avoided even through a solid ground plane.
How were you planning on testing the performance?
I need to give this further thought but if you only need 1ns worth of
control and feed one input of the LTC6957-1 with a 100 MHz sine wave,
wouldn't adjusting the level of the other input work to adjust the
delay at the output?
Hi,
My first thought would be to use a pair of couplers before and after the
delay line and bring it into a mixer to serve as a phase detector such
that you can create a control loop to stabilize delay. This way you get
a handle on the temperature variations.
There is trombone delays that can be used. They seem to reach that level
of resolution.
There is microstepper boxes, but usually they operate on 5 or 10 MHz.
There is multiple ways to design delays for CW signals, microsteppers
uses various forms of gear-boxes and programmable generators. Chips
either use gate delays or programmable comparator vs. ramp of some form.
Ensuring temperature stability and drift limits is however always an issue.
Delay loop oscillator for calibration can be done, but biases can be
problematic, so a number of different setups needs to be done to build
confidence. It's a combinatorial exercise which is quite interesting.
Cheers,
Magnus
On 02/07/2017 05:13 PM, Mattia Rizzi wrote:
Hello,
I'm looking/designing a sub-ps delay line with very high stability.
Basically it has microwave requirements on phase matching.
The main features that such delay line should have are:
- sub-ps resolution and about 1 ns range
- High stability, must not drift more than 2ps/year, preferably 1ps/year
- Temperature coefficient (tempco) below 1 ps/celsius
- Low phase noise floor, target random jitter below 100 fs RSM from 100Hz
to 1MHz. - flicker noise below -90dBc at 1Hz (100MHz carrier)
- cheap (below 50 euros) and PCB integrable
- optional: autocalibration or a way to check calibration health over time
(checking the oscillation frequency of the delay line connected as loop?)
Operating conditions: The delay line will be used for RF distribution,
where the clock signals (100-200MHz) must stay in +/- 10 ps error window.
Since timing jitter (wander) is 1.6ps RMS, the delay line must be very
accurate, with maximum of +/- 3ps of delay uncertainty. The delay line is
used to phase-match the clock outputs at factory, hence will not be
anymore modified (or for only fine corrections, tens of picoseconds). The
factory calibration compensates for the delay line and PCB
process/production variations. The boards will operate at almost same
temperature and humidity levels over years of continuous running.
Circuit constrains: The delay line is fed with an AC-coupled LVPECL clock
output (only P output used) and should provides a single-ended AC clock
output signal.
Indeed, no commercial chip fits into these requirements.
My idea is to use an RC filter to delay the input clock signal and then to
restore the clock edges with a LTC6957-1 (LVPECL outputs).
The RC filter would be realized using a varactor (Skyworks SMVA1470-004LF)
and a 16-bit DAC to control the voltage bias (+ stable voltage reference).
I already checked the values, and sub-ps resolution seems easily
achievable. The solution requires a factory calibration due to the
non-linear behavior of the varactor, but since I only need small
adjustments, this is not a problem.
The problem is to guarantee the calibration over years of operation.
Since a femtofarad parasitic capacitance can change the delay, I already
thought about protecting the delay line with some kind of resin (Epoxy?)
and/or a RF cage to protect it from dirt and moisture.
One of the issue is aging. I derived a typical varactor aging from VCTCXO
oscillators (no varactor manufacturer knows the effects of aging on its
products, apparently) and it's still good. But the aging of LTC6957 is not
known.
Is the PCB fabrication using microwave requirements on the dielectric fine?
Based on your experience, do you think that such delay line can respect the
requirements listed above, especially stability?
Am I missing something?
Thank you!
cheers,
Mattia Rizzi
time-nuts mailing list -- time-nuts@febo.com
To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts
and follow the instructions there.
Even presuming this system is for clocking within a single-board
environment, that seems like a fairly tall order for setting resolution
and long-term stability. It could be tough to keep these numbers with
temperature and supply variations in all the circuitry involved,
including the parts that ultimately receive the various clock signals.
On the other hand, making it adjustable delay-wise should be fairly easy
- almost anything you do to tweak the operating conditions of this
essentially analog system will change the delays. The trick will be to
compensate for the unwanted effects, and consistently control certain
things to set the delay.
I'd recommend using differential signals throughout, if possible, with
coarse delays set by sections of on-board transmission line, and fine
adjustment by tweaking DC bias at various points. I don't think you need
to add any extra variable delays such as varicap circuits - you should
be able to affect enough control and compensation just with the normal
part characteristics.
Ed
Hello,
thank you all for the answers!
The description I gave in the first email is a simplification of the
system. The delay line is used to phase-match the clocks of a distributed
measurement system. Each board feature an ADC and a DAC. You can see it as
a distributed RF acquisition system, with microwave requirements on phase
matching. The delay line is used ALSO to correctly align the clocks for the
ADCs, since each IC has an unknown Aperture Delay (PVT kicks in).
Unfortunately I cannot change the voltage references to introduces a
variable delay. That's also why I would like to have a delay line rather
than a set-and-forget solution: I can compensate for PVT of the ADC and DAC
as well.
About temperature variation: LTC6957-1 is excellent, 0.1ps/C of propagation
delay change. I still have to check with Linear if this figure is valid
also if you don't use BOTH (P and N) output clock lines. I'm not sure to
use a balun (such as Minicircuit ADT2-1) for differential-to-single-ended
conversion because I dont want to introduce additional tempco.
Unfortunately, Mini-circuit has no data about that. The varactor itself has
a slight tempco, but the overall tempco should be below 1 ps/C.
About voltage & supply variations: I'm planning to use a dedicate LDO for
the delay line. LTC6957-1 has a maximum of 50ps/V propagation delay
variation, I'm expecting to use an LDO with <1 mV/C of regulation
stability (LT3045 has less than 100uV over 20 degree variation, but it's a
bit expensive). Again, I don't know if the 50ps/V figure is still valid
using only one output, but since LVPECL output stages are done using a BJT
always in the active region, I'm expecting an isolation from the power
supply voltage.
@Magnus:
My first thought would be to use a pair of couplers before and after the
delay line and bring it into a mixer to serve as a phase detector such that
you can create a control loop to stabilize delay. This way you get a handle
on the temperature variations.
Thanks! Do you know a phase detector with such requirements on stability? I
checked Mini-circuit but they don't have factory data on the stability of
their products. Also, my signals are clocks rather than pure sinewaves.
@Scott
I would also advise you take a look at how well you can maintain your
system impedance, say 50 Ohms. For example, I have seen about 100's ps
phase difference on a 10 MHz reference, using one BNC female-female coupler
versus another
Yes, this is a calibration issue (repeatability) to be investigated, but
since microwave systems have the same issues I hope there's already a way
to how achieve that.
Thank you!
cheers,
Mattia
2017-02-07 23:43 GMT+01:00 Magnus Danielson magnus@rubidium.dyndns.org:
Hi,
My first thought would be to use a pair of couplers before and after the
delay line and bring it into a mixer to serve as a phase detector such that
you can create a control loop to stabilize delay. This way you get a handle
on the temperature variations.
There is trombone delays that can be used. They seem to reach that level
of resolution.
There is microstepper boxes, but usually they operate on 5 or 10 MHz.
There is multiple ways to design delays for CW signals, microsteppers uses
various forms of gear-boxes and programmable generators. Chips either use
gate delays or programmable comparator vs. ramp of some form.
Ensuring temperature stability and drift limits is however always an issue.
Delay loop oscillator for calibration can be done, but biases can be
problematic, so a number of different setups needs to be done to build
confidence. It's a combinatorial exercise which is quite interesting.
Cheers,
Magnus
On 02/07/2017 05:13 PM, Mattia Rizzi wrote:
Hello,
I'm looking/designing a sub-ps delay line with very high stability.
Basically it has microwave requirements on phase matching.
The main features that such delay line should have are:
- sub-ps resolution and about 1 ns range
- High stability, must not drift more than 2ps/year, preferably 1ps/year
- Temperature coefficient (tempco) below 1 ps/celsius
- Low phase noise floor, target random jitter below 100 fs RSM from 100Hz
to 1MHz. - flicker noise below -90dBc at 1Hz (100MHz carrier)
- cheap (below 50 euros) and PCB integrable
- optional: autocalibration or a way to check calibration health over time
(checking the oscillation frequency of the delay line connected as loop?)
Operating conditions: The delay line will be used for RF distribution,
where the clock signals (100-200MHz) must stay in +/- 10 ps error window.
Since timing jitter (wander) is 1.6ps RMS, the delay line must be very
accurate, with maximum of +/- 3ps of delay uncertainty. The delay line is
used to phase-match the clock outputs at factory, hence will not be
anymore modified (or for only fine corrections, tens of picoseconds). The
factory calibration compensates for the delay line and PCB
process/production variations. The boards will operate at almost same
temperature and humidity levels over years of continuous running.
Circuit constrains: The delay line is fed with an AC-coupled LVPECL clock
output (only P output used) and should provides a single-ended AC clock
output signal.
Indeed, no commercial chip fits into these requirements.
My idea is to use an RC filter to delay the input clock signal and then to
restore the clock edges with a LTC6957-1 (LVPECL outputs).
The RC filter would be realized using a varactor (Skyworks SMVA1470-004LF)
and a 16-bit DAC to control the voltage bias (+ stable voltage reference).
I already checked the values, and sub-ps resolution seems easily
achievable. The solution requires a factory calibration due to the
non-linear behavior of the varactor, but since I only need small
adjustments, this is not a problem.
The problem is to guarantee the calibration over years of operation.
Since a femtofarad parasitic capacitance can change the delay, I already
thought about protecting the delay line with some kind of resin (Epoxy?)
and/or a RF cage to protect it from dirt and moisture.
One of the issue is aging. I derived a typical varactor aging from VCTCXO
oscillators (no varactor manufacturer knows the effects of aging on its
products, apparently) and it's still good. But the aging of LTC6957 is not
known.
Is the PCB fabrication using microwave requirements on the dielectric
fine?
Based on your experience, do you think that such delay line can respect
the
requirements listed above, especially stability?
Am I missing something?
Thank you!
cheers,
Mattia Rizzi
time-nuts mailing list -- time-nuts@febo.com
To unsubscribe, go to https://www.febo.com/cgi-bin/m
ailman/listinfo/time-nuts
and follow the instructions there.
time-nuts mailing list -- time-nuts@febo.com
To unsubscribe, go to https://www.febo.com/cgi-bin/m
ailman/listinfo/time-nuts
and follow the instructions there.
If you make a variable delay by adding external RC (varicap) circuits,
the edges will be slower, and the amplitudes will be affected. This will
tend to complicate the detection and reshaping of the clock by the
LTC6957. Pay particular attention to page 24 and Fig 8 in the datasheet,
regarding the strong effect of input overdrive on prop delay and
symmetry. This should be considered in the design of anything added in
front.
It may be better to use this effect advantageously instead, to get
variable delay by tweaking DC bias in the right places. Depending on
which edges are ultimately used in the ADCs and DACs, you may be able to
affect all sorts of beneficial timing control - or have all sorts of
timing problems - depending on how you handle it.
Ed