I saw the same, which put me off trying to do the same. However I am not sure that your approach will work as the specs for the external clock indicate:

• EXTernal  selects an external reference signal applied to the rear panel
  Ext Ref In  connector. The signal must be:
  •  1 MHz , 5 MHz, or 10 MHz
  •  100 mVrms to 2.5 Vrms
  •  sine wave

Your output is digital, no? It may function but I wouldn’t trust it.

It is a no brainer to get a sine from a square wave, BUT , I seriously doubt that the excellent ADEV can be maintained with all that flipping and flopping going on. I even doubt that it could be kept in a pure sine implementation.

Mike

"The power of accurate observation is commonly called cynicism by those who have not got it. »
George Bernard Shaw

The URL you cited doesn't have the schematic in any obvious
place.  However, using both edges of the clock to supposedly
result in 50% duty cycle output depends on having 50%
duty cycle at the input.  If you have differential logic
like ECL, this can be realistic.  Single ended logic,
questionable.

The other issue is that the divider can start up in any
one of 3 phases with respect to any other frequency
dividers in your system, unless you do something to
synchronize the various dividers.

This is probably old hat to most readers of time-nuts, but
I just wanted to mention it in case some were unaware
of it.

Rick

On 6/8/2016 6:55 AM, Nick Sayer via time-nuts wrote:

Nick wrote:

You can achieve substantially lower jitter (phase noise) with a
regenerative divider, which also allows you to divide by 3/2 for a 10MHz
output.  I've built several like that, and they work extremely well.

There are simpler divide-by-three logic circuits (generally, the simpler
the circuit the closer to an exact 50% duty cycle and the lower the
jitter).  See the attached image for one approach.

Best regards,

Charles

On Wed, 8 Jun 2016 18:35:43 +0200
Mike Cook michael.cook@sfr.fr wrote:

I would not worry too much about ADEV degradation. The two most influencial
parameters for delay changes are temperature and supply voltage. Given that
the power supply is of decent quality (<<1% change per °C), then the supply
variations have little influence. Temperature, in an office or lab, does
not change that much to cause large differences.

I attached a TDEV plot (TDEV_all_pairs.png) of our clock sync system, which
uses Cyclone4 FPGAs (on an undmodified DE0-nano board) as TDCs to measure and
correct the skew between otherwise independent nodes. The measurements were
done using pulse outputs of the nodes feeding an DTS-2075, hence depict the
skew between pairs of nodes[1]. As you can see the curves go down nicely down
(with white phase noise) to <2ps in the 10-100s range. The blue curve looks
worse, due to hysteresis effects in the control system.

The second plot (TDEV_N4_N5_long.png) is an 9d19h run of the blue node
pair from the other plot. As you can see, the TDEV stays below 10ps up to 1e5s.
Most of the instability at taus >10 comes from the above mentioned hysteresis.

All measurements were done in late April, early May this year in Vienna,
with changing weather conditions. I.e. the temperature was anything but stable.
Unfortunately, we didn't record the temperature in the room.

If you take this data as indication, you can guess that any modern CMOS system
in an office environment will add less than 10ps timing uncertainty long term.
More likely it will be less than 1ps, as the plots depict measurements of a
complex system that does a lot of detection and non-trivial processing.
For a frequency reference that is fed by GPS this level of stability should
be good enough.

Short term effects (aka phase noise) are a totally different story, though.

		Attila Kinali

[1] I am leaving the details of the system out for the moment, as they are
not really important for the discussion at hand. As soon as I have time to
prepare the arxiv version of the paper I will post it on this list.

--
It is upon moral qualities that a society is ultimately founded. All
the prosperity and technological sophistication in the world is of no
use without that foundation.
-- Miss Matheson, The Diamond Age, Neil Stephenson

utilizing rising and falling edges makes the circuit output signal duty
cycle sensitive to the input signal's duty cycle, and therefore the
harmonic content will vary with the input duty cycle variation.
73
KJ6UHN
Alex

On 6/8/2016 9:47 AM, Richard (Rick) Karlquist wrote:

In this case, the FE-405B outputs a sine wave, which is converted to square with a self-biased inverter. That’s fed into an NB3N551 clock buffer. Two of the outputs go off to the discipline system and the other two are user outputs, one of which would be fed into the circuit in question.

On the scope, the 10 MHz I have from the FE-5680As look 50% to me, but of course that doesn’t mean a lot. The controller is clocked from it too, and it really wants “close” to 50% duty cycles, but again, their tolerances aren’t Time Nuts(tm) grade.

All that said, I’m feeding this stuff into a 53220A, so I’m not sure there aren’t bigger fish to fry...

There’s a link to the blog posting (not mine) that has the schematic on the OSHPark shared project.

The schematic there isn’t totally obvious - the square boxes that are otherwise unlabeled are D flip-flops with D on the left and Q on the right. I’ve simulated the circuit at CircuitLab and gotten the correct behavior, for what that’s worth.

You’re correct that multiple instances of this circuit fed from the same source would not be in phase. That’s ok with me. I’m just going to build one.

I don’t know if I’ll actually put it into service or not. I have lots of different references at my disposal for the 53220A, and at this point my thinking is that all of them are going to be a tie given this TIA’s specs.

Someone else mentioned sine vs square for the 53220A reference input. I’ve fed square waves into this TIA with no indication that it hasn’t worked just as well as sine, but I don’t have any assurance beyond that.

Very nice! That one also simulates properly on CircuitLab without the delay gates in the output feedback. I tried adding the delay gates back in, and it didn’t change, but I can imagine that’s just because it’s a simulator.

On 6/8/2016 9:59 AM, Charles Steinmetz wrote:

When I was at Agilent, they developed a very low noise regenerative
divide by 3/2 chain to use in high performance instruments.  The gurus
who know about this stuff said it was the lowest phase noise
architecture.

Rick