Thanks for the hints and references everyone. I'll dig in and possibly come back with some more questions. BR, James

Hi Some quick hints: 1) You need a way to digitize the phase input with adequate resolution. If you have a 1 second period and want 1 ns, you need a way to digitize at a 1:1,000,000,000 sort of level. That’s in the 30 bit range so a simple ADC isn’t going to do it alone. 2) You need a way to digitize the control output. If you have a +/- 2 ppm EFC range and a 16 bit DAC you get a LSB step around 4/65,000 = 6x10^-8. If you are after < 1x10^-9, 16 bits isn’t going to get you there all by it’s self. 3) In the middle of the two, you have a loop gain, an integrator time constant, and a bit of phase shift. That plugs into the standard equations to come up with a solution (along with the normal sensitivities that drive any PLL). Yes, there are a lot of weird issues to deal with, but conceptually there isn not a lot to it. Bob > On Mar 21, 2017, at 7:25 PM, James Peroulas <james@peroulas.com> wrote: > > Thanks for the hints and references everyone. I'll dig in and possibly come > back with some more questions. > > BR, > James > _______________________________________________ > time-nuts mailing list -- time-nuts@febo.com > To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts > and follow the instructions there.

Hi Slipped a factor of 1,000 on the DAC … sorry about that … Bob > On Mar 21, 2017, at 7:25 PM, James Peroulas <james@peroulas.com> wrote: > > Thanks for the hints and references everyone. I'll dig in and possibly come > back with some more questions. > > BR, > James > _______________________________________________ > time-nuts mailing list -- time-nuts@febo.com > To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts > and follow the instructions there.

		Attila Kinali

On Tue, 21 Mar 2017 21:45:24 -0400 Bob Camp <kb8tq@n1k.org> wrote: > 1) You need a way to digitize the phase input with adequate resolution. If > you have a 1 second period and want 1 ns, you need a way to digitize at > a 1:1,000,000,000 sort of level. That’s in the 30 bit range so a simple > ADC isn’t going to do it alone. That depends on how the phase difference is measured. If the whole measurement period needs to be encoded, then yes, the number of bits needed will make it difficult. But usually the input frequency range is limited, which allows to measure and encode just the difference between expected and actual arrival time of the pulse/edge. The integrated version of these PLLs (the ADPLL - all digitall PLL), if they have a real TDC, have only a resolution in the order of 7-8 bits (IIRC I've seen down to 4 bits). And then there is the class of those Bang-Bang PLL, which only encode one bit: early/late. Eventhough they are relatively crude and rely on the loopfilter to smooth things out, they perform quite well. Attila Kinali -- It is upon moral qualities that a society is ultimately founded. All the prosperity and technological sophistication in the world is of no use without that foundation. -- Miss Matheson, The Diamond Age, Neil Stephenson

		Attila Kinali

Hi > On Mar 22, 2017, at 7:50 AM, Attila Kinali <attila@kinali.ch> wrote: > > On Tue, 21 Mar 2017 21:45:24 -0400 > Bob Camp <kb8tq@n1k.org> wrote: > >> 1) You need a way to digitize the phase input with adequate resolution. If >> you have a 1 second period and want 1 ns, you need a way to digitize at >> a 1:1,000,000,000 sort of level. That’s in the 30 bit range so a simple >> ADC isn’t going to do it alone. > > That depends on how the phase difference is measured. If the whole > measurement period needs to be encoded, then yes, the number of > bits needed will make it difficult. But usually the input frequency > range is limited, which allows to measure and encode just the difference > between expected and actual arrival time of the pulse/edge. The integrated > version of these PLLs (the ADPLL - all digitall PLL), if they have a > real TDC, have only a resolution in the order of 7-8 bits (IIRC I've seen > down to 4 bits). And then there is the class of those Bang-Bang PLL, > which only encode one bit: early/late. Eventhough they are relatively > crude and rely on the loopfilter to smooth things out, they perform > quite well. We started out with an XOR that has a 50/50 duty cycle. An early /late process only works if you run the outputs through an ADC and calibrate them to some degree. Then you are right back to a lot of resolution time wise. Bob > > Attila Kinali > > -- > It is upon moral qualities that a society is ultimately founded. All > the prosperity and technological sophistication in the world is of no > use without that foundation. > -- Miss Matheson, The Diamond Age, Neil Stephenson > _______________________________________________ > time-nuts mailing list -- time-nuts@febo.com > To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts > and follow the instructions there.

                   Attila Kinali

This has been a great conversation as I have tinkered with classical filters forever. But the fact is with micros so cheap the flexibility they add to the loop filtering is quite nice. Essentially droop-less filters with silly time constants and then other math on the data. That may or may-not improve behaviors. Regards Paul WB8TSL On Wed, Mar 22, 2017 at 5:51 PM, Bob kb8tq <kb8tq@n1k.org> wrote: > Hi > > > > On Mar 22, 2017, at 7:50 AM, Attila Kinali <attila@kinali.ch> wrote: > > > > On Tue, 21 Mar 2017 21:45:24 -0400 > > Bob Camp <kb8tq@n1k.org> wrote: > > > >> 1) You need a way to digitize the phase input with adequate resolution. > If > >> you have a 1 second period and want 1 ns, you need a way to digitize at > >> a 1:1,000,000,000 sort of level. That’s in the 30 bit range so a simple > >> ADC isn’t going to do it alone. > > > > That depends on how the phase difference is measured. If the whole > > measurement period needs to be encoded, then yes, the number of > > bits needed will make it difficult. But usually the input frequency > > range is limited, which allows to measure and encode just the difference > > between expected and actual arrival time of the pulse/edge. The > integrated > > version of these PLLs (the ADPLL - all digitall PLL), if they have a > > real TDC, have only a resolution in the order of 7-8 bits (IIRC I've seen > > down to 4 bits). And then there is the class of those Bang-Bang PLL, > > which only encode one bit: early/late. Eventhough they are relatively > > crude and rely on the loopfilter to smooth things out, they perform > > quite well. > > We started out with an XOR that has a 50/50 duty cycle. An early /late > process only works if you run the outputs through an ADC and calibrate > them to some degree. Then you are right back to a lot of resolution time > wise. > > Bob > > > > > Attila Kinali > > > > -- > > It is upon moral qualities that a society is ultimately founded. All > > the prosperity and technological sophistication in the world is of no > > use without that foundation. > > -- Miss Matheson, The Diamond Age, Neil Stephenson > > _______________________________________________ > > time-nuts mailing list -- time-nuts@febo.com > > To unsubscribe, go to https://www.febo.com/cgi-bin/ > mailman/listinfo/time-nuts > > and follow the instructions there. > > _______________________________________________ > time-nuts mailing list -- time-nuts@febo.com > To unsubscribe, go to https://www.febo.com/cgi-bin/ > mailman/listinfo/time-nuts > and follow the instructions there. >