time-nuts@lists.febo.com

Discussion of precise time and frequency measurement

View all threads

Re: [time-nuts] More on SiLabs 5340

MG
Mark Goldberg
Mon, Jan 29, 2018 11:37 PM

Reference my earlier postings titled "SI532X Chips Close In Spurs (Somewhat
Long)". There are many sets of register values that will get you the same
output frequency and the clock builder may not give you an optimal set for
phase noise and spurs. I created a spreadsheet to calculate other sets of
values and chose one that worked the best. I just did it through trial and
error of the different sets of values I came up with until I found one with
low spurs.

73,

Mark
W7MLG

On Mon, Jan 29, 2018 at 4:16 PM, John Ackermann N8UR jra@febo.com wrote:

On 01/29/2018 04:54 PM, Chris Caudle wrote:

On Mon, January 29, 2018 2:38 pm, John Ackermann N8UR wrote:

The close-in phase noise is quite amazing, but the floor is much worse
than in free-run mode.

That phase noise plot doesn't look quite right, what PLL bandwidth did you
set?

Sorry for the earlier null reply.  I just used the settings that the
ClockBuilder software came up with (which IIRC don't offer any choices
about loop bandwidth in the "wizard").  I haven't yet dug into the register
options, but I'm sure that there are ways to optimize.

John


time-nuts mailing list -- time-nuts@febo.com
To unsubscribe, go to https://www.febo.com/cgi-bin/m
ailman/listinfo/time-nuts
and follow the instructions there.

Reference my earlier postings titled "SI532X Chips Close In Spurs (Somewhat Long)". There are many sets of register values that will get you the same output frequency and the clock builder may not give you an optimal set for phase noise and spurs. I created a spreadsheet to calculate other sets of values and chose one that worked the best. I just did it through trial and error of the different sets of values I came up with until I found one with low spurs. 73, Mark W7MLG On Mon, Jan 29, 2018 at 4:16 PM, John Ackermann N8UR <jra@febo.com> wrote: > On 01/29/2018 04:54 PM, Chris Caudle wrote: > >> On Mon, January 29, 2018 2:38 pm, John Ackermann N8UR wrote: >> >>> The close-in phase noise is quite amazing, but the floor is much worse >>> than in free-run mode. >>> >> >> That phase noise plot doesn't look quite right, what PLL bandwidth did you >> set? >> > > Sorry for the earlier null reply. I just used the settings that the > ClockBuilder software came up with (which IIRC don't offer any choices > about loop bandwidth in the "wizard"). I haven't yet dug into the register > options, but I'm sure that there are ways to optimize. > > John > > _______________________________________________ > time-nuts mailing list -- time-nuts@febo.com > To unsubscribe, go to https://www.febo.com/cgi-bin/m > ailman/listinfo/time-nuts > and follow the instructions there. >
J
jimlux
Tue, Jan 30, 2018 12:04 AM

On 1/29/18 3:37 PM, Mark Goldberg wrote:

Reference my earlier postings titled "SI532X Chips Close In Spurs (Somewhat
Long)". There are many sets of register values that will get you the same
output frequency and the clock builder may not give you an optimal set for
phase noise and spurs. I created a spreadsheet to calculate other sets of
values and chose one that worked the best. I just did it through trial and
error of the different sets of values I came up with until I found one with
low spurs.

We've experienced that here with other PLL chips - For the ADF4108
integer-N PLL, sometimes there's a big difference between R odd and R
even (the R is the reference divisor in the fout = fin * (M*B+A)/R

So you wind up fooling around with various combinations of A, B, and R
to get the spurs where you want them (or, more commonly, to move them
from where you don't want them)

On 1/29/18 3:37 PM, Mark Goldberg wrote: > Reference my earlier postings titled "SI532X Chips Close In Spurs (Somewhat > Long)". There are many sets of register values that will get you the same > output frequency and the clock builder may not give you an optimal set for > phase noise and spurs. I created a spreadsheet to calculate other sets of > values and chose one that worked the best. I just did it through trial and > error of the different sets of values I came up with until I found one with > low spurs. > We've experienced that here with other PLL chips - For the ADF4108 integer-N PLL, sometimes there's a big difference between R odd and R even (the R is the reference divisor in the fout = fin * (M*B+A)/R So you wind up fooling around with various combinations of A, B, and R to get the spurs where you want them (or, more commonly, to move them from where you don't want them)