Hi

Assuming you are trying to extract timing from the signal (time ticks on WWVB), the
downconversion really does not matter. The ADC samples are what will “tag” your
time data. If you are trying to extract frequency from the signal (you are after the center
frequency of WWVB) then both the offset oscillator and the ADC clock will matter:

Your baseband tone is Fwwvb - Flo = Fif
Your estimate of that tone is based on the frequency of the ADC samples.

Bob

It would be (as you point out) a bad idea to have the the ADC sampling rate
to be exactly the same as the downconversion oscillator.

In many cases they would both be derived from the same master oscillator.
But the ratios would be consciously chosen to not be simple integer
multiple relations so beating between the ADC and the downconversion
oscillator would get washed out.

This issue of avoiding simple harmonic relationships between receiver
oscillators (and samplers) long predates digital radios, it is a goal in
any superhet to avoid "birdies".

Tim N3QE

On Sat, Dec 23, 2017 at 9:46 AM, Stephan Sandenbergh <ssandenbergh@gmail.com

Oops, I noted a sign error in the previous diagram. The attached seems
better...

On Sat, Dec 23, 2017 at 4:46 PM Stephan Sandenbergh ssandenbergh@gmail.com
wrote:

Hi

What is the Time Nut goal here? Are we after the carrier frequency or after the
modulation on the signal?

Bob

Hi,

The goal would be to be able to tell what the phase and frequency of the
down-converted and sampled signal is. So no modulation on the carrier (for
now).

So given the RF signal is perfect sinusoid, and given that you know the
parameters x(t) = xo + yot (time and fractional frequency offset) of the
reference oscillator, one should be able to determine the phase and
frequency of the ADC output at any given time (in a perfect world).

In general, the ADC sampling frequency (and the LO frequency for that
matter) could be at non-integer multiples of the reference oscilator.
However, both the LO and sampling frequency will be a derivative of the
reference and will have the x(t) = xo + yot time and frequency offset.
Hence, that should be accounted for in both down-conversion and ADC
sampling.

However, I have not seen examples where time and frequency offsets have
been included in the ADC sampling. But, it seems logical that reference
oscillator's imperfections modulate both the down-conversion and the ADC
timebase.

I guess I'm just worried that I might be missing something obvious here?
And I know there is no better place to ask such a question other than on
time-nuts :)

Regards,

Stephan

On Sat, 23 Dec 2017 at 18:11 Bob kb8tq kb8tq@n1k.org wrote:

On Sat, 23 Dec 2017 21:00:39 +0000
Stephan Sandenbergh ssandenbergh@gmail.com wrote:

No, your derivation is correct. Though conventionally, it would be
written as: V_{IF}(t) = sin[(ω_{RF} - ω_{LO})t - Δφ_{RF-LO}(t)]
Hence, the sampled signal becomes:
V_{IF}[nT_s] = sin[(ω_{RF}(nT_s) - ω_{LO}(nT_s) - Δφ_{RF-LO}[nTS]]

In this notation, it is a bit more obvious what's going on. Assuming
both RF and LO frequency are constant, then the sampled voltage only
depends on the difference of the frequencies, and the initial phase offset
at time t = 0*T_s. Be aware that this only holds true if you either
use a low pass filter after the mixer or use complex down conversion.
In all other cases you have to account for the (ω_{RF} + ω_{LO}) component
as well.

Using x(t) = x_0 + y_0*t confuses things a bit, as this means
that you are modulating the phase with a frequency of y_0, which you
probably do not intend.

Any phase noise you have in the system, you can fold into φ_{RF-LO}(t).

Please note, the above has the implicit assumption, that:
ω_{IF} is < 0.5 * ω_{LO}, ie that the IF signal is in the first
Nyquist zone. Otherwise you have to treat the ADC as another mixer stage,
with it's own ω_{LO_{ADC}} and φ_{LO_{ADC}}.

As Tim Shoppa mentioned, you do not want to have a ratio with small integers
between the LO frequency and the sampling frequency, as any feedthrough of
the LO and its harmonics will lead to a DC offset and spurs. The amplitude
of both will depend on the exact phase relation between the LO frequency
and the sampling frequency, which is usually stable, but not time-nuts stable.

			Attila Kinali

--
It is upon moral qualities that a society is ultimately founded. All
the prosperity and technological sophistication in the world is of no
use without that foundation.
-- Miss Matheson, The Diamond Age, Neil Stephenson

Hi,

A happy New Year to you all!

Also, thank you to everyone who replied in such detail. It is always a
privilege being able to bounce ideas off of the time-nuts community.

I have found that it is often the case that the error introduced by ADC
sampling is ignored. However, there is an error introduced during
down-conversion and the ADC (with its imperfect time base) then samples
both the resultant IF signal and the IF error term. The result is a
complicated error when frequency offset, drift and random effects are
included.

I plotted the result for a few oscillator drift rate values. It seems that
the 'extra' error introduced by the imperfect ADC time base would be
negligible for many applications for OCXO drift rates or better. This is
likely the reason why it is often ignored.

I'm glad I understand it better now.

Regards,

Stephan.

On Mon, Dec 25, 2017 at 3:11 AM Attila Kinali attila@kinali.ch wrote:

Am 11.01.2018 um 10:57 schrieb Stephan Sandenbergh:

There is no reason to assume that an ADC time base should be more
imperfect than a down converter time base.

No, what I really want is having no LO frequency at all. I'd like to
start with a Pascall
class 100 MHz osc, maybe locked to the house reference. Multiply up to
800, 1200 or
2400 MHz using barndoor-wide filters that have a constant delay on the
center frequency.
The spurii are 100 MHz far away or multiples thereof at the later stages.

The ADC would be an Analog Devices AD9680, AD9208 or similar from TI.
These are
dual ADCs already, with 2 of them we could play most of the tricks of
the Timepod,
just sampling directly in L-band included.

Use the built-in DDS and down converters with small integers that
produce no birdies.
Filter and decimate like hell. Here we get the phase noise performance
back that we
have lost in  multiplication. This down conversion/filtering/decimation
is available twice
in each ADC chip, no need for DIY.

When we have long words at a comfortably slow sample rate, we can
transfer them
via the JESD204B links to a mid size ZYNC system on chip, for further
processing in
its FPGA and/or CPUs, with Linux, network access and all the comfort we
are used to.

There are also interpolating/up sampling DACs for the transmitter if
needed. The
G5 phone system gives us nice building blocks to play with.
That all would fit on a 3*5 inch board, like some Red Pitaya on steroids.

<  http://www.analog.com/en/search.html?q=ad9680   >
<  https://www.redpitaya.com/c96/stemsuplabsup-125-14   >

cheers, Gerhard