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Re: [time-nuts] HP-531xx calibrator nearing completion

CC
Chris Caudle
Fri, Sep 8, 2017 6:25 PM

On Thu, September 7, 2017 10:56 am, Mark Sims wrote:

It takes a 10 MHz input,  feeds it through a sine-to square converter
(using a biased CMOS gate) doubles it to 20 MHz using  XOR gates,

Could you send me a snip of what that looks like?  Or a link to the
schematic if you have it already.  I need to take 10MHz in and was going
to generate 24MHz with a PLL, but probably 20MHz will be acceptable, and I
think just a couple of gates would work a lot better from a space and
power layout perspective.

If I need 50/50 duty cycle I would need to double again to 40MHz and use a
flip-flop to divide by 2, right?  Does the XOR circuit still work OK with
a narrow duty cycle?

thanks,
Chris Caudle

On Thu, September 7, 2017 10:56 am, Mark Sims wrote: > It takes a 10 MHz input, feeds it through a sine-to square converter > (using a biased CMOS gate) doubles it to 20 MHz using XOR gates, Could you send me a snip of what that looks like? Or a link to the schematic if you have it already. I need to take 10MHz in and was going to generate 24MHz with a PLL, but probably 20MHz will be acceptable, and I think just a couple of gates would work a lot better from a space and power layout perspective. If I need 50/50 duty cycle I would need to double again to 40MHz and use a flip-flop to divide by 2, right? Does the XOR circuit still work OK with a narrow duty cycle? thanks, Chris Caudle
CS
Charles Steinmetz
Fri, Sep 8, 2017 10:15 PM

Chris wrote:

Mark Sims wrote:

It takes a 10 MHz input,  feeds it through a sine-to square converter
(using a biased CMOS gate)

Could you send me a snip of what that looks like?

Depending on your application and its tolerance for jitter/PN, you may
want to use a fast analog comparator to do the initial sine-square
conversion.  The difference in jitter/PN compared to a biased CMOS gate
can be 10-20dB over a wide range of tau/BW (even worse if the gate has a
Schmidt trigger input, which has WAY, WAY too much hysteresis for a
sine-square converter).  I recommend the TLV3501, LT1719, and LT1720 out
of extensive experience with them.  These comparators have just the
right amount of internal hysteresis for squaring a 10MHz sine wave, with
10MHz jitter around 10-15pSrms for jitter bandwidths from 10Hz-5MHz.

Of course, if your multiplier/divider chain has more jitter than a CMOS
squarer, it won't make much difference which squarer you use -- so be
careful with its design and construction.

Best regards,

Charles

Chris wrote: > Mark Sims wrote: >> It takes a 10 MHz input, feeds it through a sine-to square converter >> (using a biased CMOS gate) > > Could you send me a snip of what that looks like? Depending on your application and its tolerance for jitter/PN, you may want to use a fast analog comparator to do the initial sine-square conversion. The difference in jitter/PN compared to a biased CMOS gate can be 10-20dB over a wide range of tau/BW (even worse if the gate has a Schmidt trigger input, which has WAY, WAY too much hysteresis for a sine-square converter). I recommend the TLV3501, LT1719, and LT1720 out of extensive experience with them. These comparators have just the right amount of internal hysteresis for squaring a 10MHz sine wave, with 10MHz jitter around 10-15pSrms for jitter bandwidths from 10Hz-5MHz. Of course, if your multiplier/divider chain has more jitter than a CMOS squarer, it won't make much difference which squarer you use -- so be careful with its design and construction. Best regards, Charles
N
Neil
Fri, Sep 8, 2017 10:56 PM

I've used some LT1719s in a project to discipline a 100MHz OCXO using an
HMC1031. They work really well in squaring up the 10MHz sine from my Rb
reference.

Neil G4DBN

On 08/09/2017 23:15, Charles Steinmetz wrote:

Chris wrote:

Mark Sims wrote:

It takes a 10 MHz input,  feeds it through a sine-to square converter
(using a biased CMOS gate)

Could you send me a snip of what that looks like?

Depending on your application and its tolerance for jitter/PN, you may
want to use a fast analog comparator to do the initial sine-square
conversion.  The difference in jitter/PN compared to a biased CMOS
gate can be 10-20dB over a wide range of tau/BW (even worse if the
gate has a Schmidt trigger input, which has WAY, WAY too much
hysteresis for a sine-square converter).  I recommend the TLV3501,
LT1719, and LT1720 out of extensive experience with them.  These
comparators have just the right amount of internal hysteresis for
squaring a 10MHz sine wave, with 10MHz jitter around 10-15pSrms for
jitter bandwidths from 10Hz-5MHz.

Of course, if your multiplier/divider chain has more jitter than a
CMOS squarer, it won't make much difference which squarer you use --
so be careful with its design and construction.

Best regards,

Charles


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I've used some LT1719s in a project to discipline a 100MHz OCXO using an HMC1031. They work really well in squaring up the 10MHz sine from my Rb reference. Neil G4DBN On 08/09/2017 23:15, Charles Steinmetz wrote: > Chris wrote: > >> Mark Sims wrote: >>> It takes a 10 MHz input,  feeds it through a sine-to square converter >>> (using a biased CMOS gate) >> >> Could you send me a snip of what that looks like? > > Depending on your application and its tolerance for jitter/PN, you may > want to use a fast analog comparator to do the initial sine-square > conversion.  The difference in jitter/PN compared to a biased CMOS > gate can be 10-20dB over a wide range of tau/BW (even worse if the > gate has a Schmidt trigger input, which has WAY, WAY too much > hysteresis for a sine-square converter).  I recommend the TLV3501, > LT1719, and LT1720 out of extensive experience with them.  These > comparators have just the right amount of internal hysteresis for > squaring a 10MHz sine wave, with 10MHz jitter around 10-15pSrms for > jitter bandwidths from 10Hz-5MHz. > > Of course, if your multiplier/divider chain has more jitter than a > CMOS squarer, it won't make much difference which squarer you use -- > so be careful with its design and construction. > > Best regards, > > Charles > > > _______________________________________________ > time-nuts mailing list -- time-nuts@febo.com > To unsubscribe, go to > https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts > and follow the instructions there.
CC
Chris Caudle
Sat, Sep 9, 2017 1:59 AM

On Fri, September 8, 2017 5:15 pm, Charles Steinmetz wrote:

Depending on your application and its tolerance for jitter/PN, you may
want to use a fast analog comparator to do the initial sine-square
conversion.

I think there have been several discussions on squaring circuits, I was
more interested in the XOR doubler.  That seems like it might be pretty
simple to implement since I will have power supplies for CMOS gates easily
available.  I don't remember seeing discussions on that technique.

--
Chris Caudle

On Fri, September 8, 2017 5:15 pm, Charles Steinmetz wrote: > Depending on your application and its tolerance for jitter/PN, you may > want to use a fast analog comparator to do the initial sine-square > conversion. I think there have been several discussions on squaring circuits, I was more interested in the XOR doubler. That seems like it might be pretty simple to implement since I will have power supplies for CMOS gates easily available. I don't remember seeing discussions on that technique. -- Chris Caudle
BK
Bob kb8tq
Sat, Sep 9, 2017 2:29 AM

Hi

Quick and simple on the XOR doubler:

Buffer up your square wave. Output goes direct to one input of the XOR. Other
input goes through a filter to give you a phase shift. Low pass is one option. Band
pass is another option. Both benefit from being tunable. Net result is that you can get
the sub-harmonics down to about the -40 db level. Phase noise will floor out at whatever
the floor of the logic you use is. ( = it’s not magic)

Bob

On Sep 8, 2017, at 9:59 PM, Chris Caudle chris@chriscaudle.org wrote:

On Fri, September 8, 2017 5:15 pm, Charles Steinmetz wrote:

Depending on your application and its tolerance for jitter/PN, you may
want to use a fast analog comparator to do the initial sine-square
conversion.

I think there have been several discussions on squaring circuits, I was
more interested in the XOR doubler.  That seems like it might be pretty
simple to implement since I will have power supplies for CMOS gates easily
available.  I don't remember seeing discussions on that technique.

--
Chris Caudle


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Hi Quick and simple on the XOR doubler: Buffer up your square wave. Output goes direct to one input of the XOR. Other input goes through a filter to give you a phase shift. Low pass is one option. Band pass is another option. Both benefit from being tunable. Net result is that you can get the sub-harmonics down to about the -40 db level. Phase noise will floor out at whatever the floor of the logic you use is. ( = it’s not magic) Bob > On Sep 8, 2017, at 9:59 PM, Chris Caudle <chris@chriscaudle.org> wrote: > > On Fri, September 8, 2017 5:15 pm, Charles Steinmetz wrote: >> Depending on your application and its tolerance for jitter/PN, you may >> want to use a fast analog comparator to do the initial sine-square >> conversion. > > I think there have been several discussions on squaring circuits, I was > more interested in the XOR doubler. That seems like it might be pretty > simple to implement since I will have power supplies for CMOS gates easily > available. I don't remember seeing discussions on that technique. > > -- > Chris Caudle > > > _______________________________________________ > time-nuts mailing list -- time-nuts@febo.com > To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts > and follow the instructions there.