NCOCXO anyone?
On Sun, 24 Jul 2016 19:17:29 -0500
David davidwhess@gmail.com wrote:
There has to be a better way to do this. Maybe we could build a
wooden badger ...
What? Has the wooden rabbit failed?
As I said, I looked into this some time ago and I couldn't come up
with any "easy" way to build a DAC with more than 20 (real) bits that
has a sampling rate higher than a couple of Hz. Even what the audio
people do, if they do not use of the shelf snake-oil DACs is pretty
hard core tech (and smells even more like snake oil)... nothing you'd
do ony your kitchen table. Somehow building your own atomic frequency
standard looked easier than doing your own high precision DAC.
If anyone has a good idea how to build a DAC with more than 20bit
that is somewhat DC stable (better than ~1ppm within an hour should
be enough), i'd like to hear about that.
Attila Kinali
--
Malek's Law:
Any simple idea will be worded in the most complicated way.
On Sun, 24 Jul 2016 23:48:05 -0400
Scott Stobbe scott.j.stobbe@gmail.com wrote:
I doubt the AD5791 does much better than 16 bits operating at 1 Msps, when
you include glitch energy, noise, and distortion.
What makes you think so?
Yes, if you are using the full 500kHz bandwidth then the rms noise voltage
will be 5uV.. or 35uVp-p. But even just going down to a 1kHz bandwith
gives 235nVrms/1.5uVp-p (plus 1/f noise of 1.1uVp-p). So we are within
the 1ppm for any output larger than ~2V.
The DNL and INL are low enough that I don't think they cause any more
trouble then you'd expect from a DAC normally.
I don't know how to make use of the glitch specs and turn them
precision values.
Attila Kinali
--
Malek's Law:
Any simple idea will be worded in the most complicated way.
As a clarification, the AD5791 is the minimum implementation of a DAC, it's
merely a resistor array with SPI controllable switches. (But an impressive
set of resistors, no doubt. Maybe with a dash of secret sauce in digital
calibration). The only guaranteed specs for the AD5791 are at DC,
everything else is up to the designer.
The thermal noise of the AD5791 is 4.07 nV/rtHz * sqrt( 3.4 ) = 7.5 nV/rtHz
(same as spec'd), where 3.4 is the nominal output resistance in kOhms.
Flicker noise is due to the voltage reference, reference buffers, and post
DAC buffer.
The settling time after code transition is complete, is based of the load
capacitance as seen by the DAC, and the buffer amplifier's transient
response. The settling time of a pole to +- 0.5 ppm is 15 time constants.
Even the sample application circuit only achieved a THD of 97 dB for a 1
kHz tone, which is equivalent to 16 bits.
The INL/DNL are measured at DC, if you were to measure the INL/DNL at 1Msps
on a half bit code across span (dither 1 LSB), the results would be
dramatically different due to glitching on code transition. That being
said, they are kept separate not to confuse sources of error.
20 effective bits is 122 dB signal to every thing else.
On Mon, Jul 25, 2016 at 7:40 PM, Attila Kinali attila@kinali.ch wrote:
On Sun, 24 Jul 2016 23:48:05 -0400
Scott Stobbe scott.j.stobbe@gmail.com wrote:
I doubt the AD5791 does much better than 16 bits operating at 1 Msps,
when
you include glitch energy, noise, and distortion.
What makes you think so?
Yes, if you are using the full 500kHz bandwidth then the rms noise voltage
will be 5uV.. or 35uVp-p. But even just going down to a 1kHz bandwith
gives 235nVrms/1.5uVp-p (plus 1/f noise of 1.1uVp-p). So we are within
the 1ppm for any output larger than ~2V.
The DNL and INL are low enough that I don't think they cause any more
trouble then you'd expect from a DAC normally.
I don't know how to make use of the glitch specs and turn them
precision values.
Attila Kinali
--
Malek's Law:
Any simple idea will be worded in the most complicated way.
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On 7/25/2016 10:42 PM, Scott Stobbe wrote:
dramatically different due to glitching on code transition. That being
said, they are kept separate not to confuse sources of error.
FWIW:
The 5071A has a "home brew" DDS that was designed by the late
(and great) Robin Giffard. He used what he called a "blanking"
circuit that disconnected the DAC during the time period when it
is at risk for glitching on code transitions. He described it
in terms of some new innovation he had invented. It seemed to
me an "obvious" (that loaded word) idea that surely must have
been used before. In any event, he was clearly doing something
right (as usual).
Rick
In message 2ea1326f-0690-6884-8fc4-29f45c57fd7b@karlquist.com, "Richard (Rick
) Karlquist" writes:
The 5071A has a "home brew" DDS that was designed by the late
(and great) Robin Giffard. He used what he called a "blanking"
circuit that disconnected the DAC during the time period when it
is at risk for glitching on code transitions. He described it
in terms of some new innovation he had invented. It seemed to
me an "obvious" (that loaded word) idea that surely must have
been used before.
For instance on page 66 in HP Journal february 1989 ?
--
Poul-Henning Kamp | UNIX since Zilog Zeus 3.20
phk@FreeBSD.ORG | TCP/IP since RFC 956
FreeBSD committer | BSD since 4.3-tahoe
Never attribute to malice what can adequately be explained by incompetence.
The first reference at hand I checked was the ADI Data Converter Handbook,
1986. Pg 60 Discusses track & hold, with a reference to the HDD-1206 as
including track/hold on die.
On Tue, Jul 26, 2016 at 2:46 PM, Richard (Rick) Karlquist <
richard@karlquist.com> wrote:
On 7/25/2016 10:42 PM, Scott Stobbe wrote:
dramatically different due to glitching on code transition. That being
said, they are kept separate not to confuse sources of error.
FWIW:
The 5071A has a "home brew" DDS that was designed by the late
(and great) Robin Giffard. He used what he called a "blanking"
circuit that disconnected the DAC during the time period when it
is at risk for glitching on code transitions. He described it
in terms of some new innovation he had invented. It seemed to
me an "obvious" (that loaded word) idea that surely must have
been used before. In any event, he was clearly doing something
right (as usual).
Rick
time-nuts mailing list -- time-nuts@febo.com
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and follow the instructions there.
The concept of track & hold was well understood in 1966 and documented in the classic Philbrick Researches amplifier application book, now available at http://www.analog.com/library/analogdialogue/archives/philbrick/computing_amplifiers.html
Bob LaJeunesse
Sent: Wednesday, July 27, 2016 at 2:15 PM
From: "Scott Stobbe" scott.j.stobbe@gmail.com
To: "Discussion of precise time and frequency measurement" time-nuts@febo.com
Subject: Re: [time-nuts] Precision DACs
The first reference at hand I checked was the ADI Data Converter Handbook,
1986. Pg 60 Discusses track & hold, with a reference to the HDD-1206 as
including track/hold on die.
On Tue, Jul 26, 2016 at 2:46 PM, Richard (Rick) Karlquist <
richard@karlquist.com> wrote:
On 7/25/2016 10:42 PM, Scott Stobbe wrote:
dramatically different due to glitching on code transition. That being
said, they are kept separate not to confuse sources of error.
FWIW:
The 5071A has a "home brew" DDS that was designed by the late
(and great) Robin Giffard. He used what he called a "blanking"
circuit that disconnected the DAC during the time period when it
is at risk for glitching on code transitions. He described it
in terms of some new innovation he had invented. It seemed to
me an "obvious" (that loaded word) idea that surely must have
been used before. In any event, he was clearly doing something
right (as usual).
Rick
On Wednesday, July 27, 2016 08:55:20 PM Robert LaJeunesse wrote:
The concept of track & hold was well understood in 1966 and documented in
the classic Philbrick Researches amplifier application book, now available
at
http://www.analog.com/library/analogdialogue/archives/philbrick/computing_a
mplifiers.html
Bob LaJeunesse
Sent: Wednesday, July 27, 2016 at 2:15 PM
From: "Scott Stobbe" scott.j.stobbe@gmail.com
To: "Discussion of precise time and frequency measurement"
time-nuts@febo.com Subject: Re: [time-nuts] Precision DACs
The first reference at hand I checked was the ADI Data Converter Handbook,
1986. Pg 60 Discusses track & hold, with a reference to the HDD-1206 as
including track/hold on die.
On Tue, Jul 26, 2016 at 2:46 PM, Richard (Rick) Karlquist <
richard@karlquist.com> wrote:
On 7/25/2016 10:42 PM, Scott Stobbe wrote:
dramatically different due to glitching on code transition. That being
said, they are kept separate not to confuse sources of error.
FWIW:
The 5071A has a "home brew" DDS that was designed by the late
(and great) Robin Giffard. He used what he called a "blanking"
circuit that disconnected the DAC during the time period when it
is at risk for glitching on code transitions. He described it
in terms of some new innovation he had invented. It seemed to
me an "obvious" (that loaded word) idea that surely must have
been used before. In any event, he was clearly doing something
right (as usual).
Rick
time-nuts mailing list -- time-nuts@febo.com
To unsubscribe, go to
https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the
instructions there.
For the particular application a track and hold circuit is not necessary a
much simpler circuit that merely disconnects the DAC from the filter input and
connects the filter input to ground will suffice.
This would result if done properly in a set of constant amplitude glitches at
the sample rate which can easily be rejected by the reconstruction filter.
The DAC output in effect would be modulated by a square wave with a duty cycle
and phase with respect to DAC transitions selected to remove DAC glitches from
the filter input. The only effect of this modulation on the filtered output
signal will be a small reduction in amplitude to that achievable with a sample
and hold style deglitcher.
Bruce