Empathy List Archives

LB

Leo Bodnar

Wed, Nov 29, 2017 9:24 PM

I am looking for an established and widely accepted procedure for verifying performance of high resolution time counters.

I have designed a time stamping counter for qualifying 1PPS signal performance against external reference (e.g. 10MHz master clock.)

Simple design verification check I am doing at the moment is gating random selection of master clock edges back into device's signal input and letting the device measure this test signal offset against its reference clock - which, for ideal design, should result in zero offset (modulo 100ns.) My results are roughly in line with what I expect to see http://leobodnar.com/balloons/NTP/time-sampler-test1.png

Now, what would be recognised procedure for sweeping external input pulse delay over few hundred ns in a controlled, measurable and repeatable way?

I can see few naïve approaches:

Using selectively gated (or divided) reference clock followed by adjustable delay line. E.g. something like mechanically adjusted delay lines used in HP test sets. Or, perhaps, calibrated rigid coax sections?
Slightly offset another master clock (e.g. second Rb oscillator) gated in a similar way but without delay line, followed by statistical data analysis
Trusted pulse generator with high resolution delay adjustment fed from the same master clock as the counter

I am looking for something with ~10ps accuracy, 100ns+ range, and reasonably low jitter (~5ps or better.)
It is possible that the range needs to be split up (e.g. fixed rigid coax delay line followed by a mechanically adjust section.)

This is a low budget fun project so something simple and common sense is preferred to "price on application" NIST traceable equipment.

Thanks!
Leo

I am looking for an established and widely accepted procedure for verifying performance of high resolution time counters. I have designed a time stamping counter for qualifying 1PPS signal performance against external reference (e.g. 10MHz master clock.) Simple design verification check I am doing at the moment is gating random selection of master clock edges back into device's signal input and letting the device measure this test signal offset against its reference clock - which, for ideal design, should result in zero offset (modulo 100ns.) My results are roughly in line with what I expect to see http://leobodnar.com/balloons/NTP/time-sampler-test1.png Now, what would be recognised procedure for sweeping external input pulse delay over few hundred ns in a controlled, measurable and repeatable way? I can see few naïve approaches: 1) Using selectively gated (or divided) reference clock followed by adjustable delay line. E.g. something like mechanically adjusted delay lines used in HP test sets. Or, perhaps, calibrated rigid coax sections? 2) Slightly offset another master clock (e.g. second Rb oscillator) gated in a similar way but without delay line, followed by statistical data analysis 3) Trusted pulse generator with high resolution delay adjustment fed from the same master clock as the counter I am looking for something with ~10ps accuracy, 100ns+ range, and reasonably low jitter (~5ps or better.) It is possible that the range needs to be split up (e.g. fixed rigid coax delay line followed by a mechanically adjust section.) This is a low budget fun project so something simple and common sense is preferred to "price on application" NIST traceable equipment. Thanks! Leo

MD

Magnus Danielson

Wed, Nov 29, 2017 9:45 PM

Hi Leo,

On 11/29/2017 10:24 PM, Leo Bodnar wrote:

I am looking for an established and widely accepted procedure for verifying performance of high resolution time counters.

<snip>

Now, what would be recognised procedure for sweeping external input pulse delay over few hundred ns in a controlled, measurable and repeatable way?

I can see few naïve approaches:

Using selectively gated (or divided) reference clock followed by adjustable delay line. E.g. something like mechanically adjusted delay lines used in HP test sets. Or, perhaps, calibrated rigid coax sections?

This is not very useful in practice, except for certain tests.

Slightly offset another master clock (e.g. second Rb oscillator) gated in a similar way but without delay line, followed by statistical data analysis

Using an oscillator to syntesize a somewhat offset frequency works very
well and is established. If you have a frequency synthesizer that you
can lock to 10 MHz you should be just fine. If you set it to 9,999 MHz
the period will be 100,010 ns, that is 10 ps larger than the 10 MHz.
While you may not trigger on each occurrence, the time difference sweeps
through the full range of time relationships within 1 ms and then it
re-occurs. By collecting lots of samples, you can histogram in 10 ps
bins and make analysis. It is also trivial to measure RMS performance.
Set the synthesis for 9,9999 MHz for 1 ps sweep.

Proven in battle. You can use relatively cheap equipment for this.

Some relatively cheap DDS-board may pull this off too.

Trusted pulse generator with high resolution delay adjustment fed from the same master clock as the counter

This works too. I think it may be hard to push it very deeply down. I
have 50 ps and 5 ps resolution versions for this purpose. May be a
complementary solution to the offset generator above.

I am looking for something with ~10ps accuracy, 100ns+ range, and reasonably low jitter (~5ps or better.)
It is possible that the range needs to be split up (e.g. fixed rigid coax delay line followed by a mechanically adjust section.)

This is a low budget fun project so something simple and common sense is preferred to "price on application" NIST traceable equipment.

I hope that you can feel inspired to quickly locate the equipment needed.

Good luck and report back on your progress!

Cheers,
Magnus

Hi Leo, On 11/29/2017 10:24 PM, Leo Bodnar wrote: > I am looking for an established and widely accepted procedure for verifying performance of high resolution time counters. <snip> > Now, what would be recognised procedure for sweeping external input pulse delay over few hundred ns in a controlled, measurable and repeatable way? > > I can see few naïve approaches: > 1) Using selectively gated (or divided) reference clock followed by adjustable delay line. E.g. something like mechanically adjusted delay lines used in HP test sets. Or, perhaps, calibrated rigid coax sections? This is not very useful in practice, except for certain tests. > 2) Slightly offset another master clock (e.g. second Rb oscillator) gated in a similar way but without delay line, followed by statistical data analysis Using an oscillator to syntesize a somewhat offset frequency works very well and is established. If you have a frequency synthesizer that you can lock to 10 MHz you should be just fine. If you set it to 9,999 MHz the period will be 100,010 ns, that is 10 ps larger than the 10 MHz. While you may not trigger on each occurrence, the time difference sweeps through the full range of time relationships within 1 ms and then it re-occurs. By collecting lots of samples, you can histogram in 10 ps bins and make analysis. It is also trivial to measure RMS performance. Set the synthesis for 9,9999 MHz for 1 ps sweep. Proven in battle. You can use relatively cheap equipment for this. Some relatively cheap DDS-board may pull this off too. > 3) Trusted pulse generator with high resolution delay adjustment fed from the same master clock as the counter This works too. I think it may be hard to push it very deeply down. I have 50 ps and 5 ps resolution versions for this purpose. May be a complementary solution to the offset generator above. > I am looking for something with ~10ps accuracy, 100ns+ range, and reasonably low jitter (~5ps or better.) > It is possible that the range needs to be split up (e.g. fixed rigid coax delay line followed by a mechanically adjust section.) > > This is a low budget fun project so something simple and common sense is preferred to "price on application" NIST traceable equipment. I hope that you can feel inspired to quickly locate the equipment needed. Good luck and report back on your progress! Cheers, Magnus

PK

Poul-Henning Kamp

Wed, Nov 29, 2017 9:51 PM

In message 5602C647-1251-4D78-B82E-798BFCD8BF29@leobodnar.com, Leo Bodnar writes:

Now, what would be recognised procedure for sweeping external input pulse delay over few hundred ns in a controlled, measurable and repeatable way?

When I did this (20 years ago :-), I used a signal generator.

Lock it to the same frequency as your reference signal, but set it
for pure sine output slightly offset in frequency (10.000010/9.999990
MHz), so that your know your TI sweeps the entire window.

Until you get a god "box" distribution, there is no need to do
anything more complicated.

Be aware that flaws in the box shape can come from either the sig-gen
or your counter: This is basically a "vernier" style of measurement,
and very few sources hold up to that kind of scrutiny.

Next run as high a sampling rate as your device supports and look
for samples which "leap-frog" each other, in theory you should have
none.

Next, siggen=ref frequency, but adjust the phase (relative to
the common clock reference) and the amplitude, and see if the
zero-crossings behave the way you expect. In particular
check if the noise (= stddev) is even throughout the window.

Finally you can use PM/AM/FM modulation with different shapes
(triangle, square, sine etc) and idicies of modulation, in
each case you can calculate what distribution to expect.

While it is tempting and probably easiest to use a DDS style
generator, I recommend a synthesized one instead, to avoid
trouble with numeric spurs.

The HP3336 with its outstanding level-control is a much
overlooked bargain for this kind of stuff.

Poul-Henning

--
Poul-Henning Kamp | UNIX since Zilog Zeus 3.20
phk@FreeBSD.ORG | TCP/IP since RFC 956
FreeBSD committer | BSD since 4.3-tahoe
Never attribute to malice what can adequately be explained by incompetence.

-------- In message <5602C647-1251-4D78-B82E-798BFCD8BF29@leobodnar.com>, Leo Bodnar writes: >Now, what would be recognised procedure for sweeping external input pulse delay over few hundred ns in a controlled, measurable and repeatable way? When I did this (20 years ago :-), I used a signal generator. Lock it to the same frequency as your reference signal, but set it for pure sine output slightly offset in frequency (10.000010/9.999990 MHz), so that your know your TI sweeps the entire window. Until you get a god "box" distribution, there is no need to do anything more complicated. Be aware that flaws in the box shape can come from either the sig-gen or your counter: This is basically a "vernier" style of measurement, and very few sources hold up to that kind of scrutiny. Next run as high a sampling rate as your device supports and look for samples which "leap-frog" each other, in theory you should have none. Next, siggen=ref frequency, but adjust the phase (relative to the common clock reference) and the amplitude, and see if the zero-crossings behave the way you expect. In particular check if the noise (= stddev) is even throughout the window. Finally you can use PM/AM/FM modulation with different shapes (triangle, square, sine etc) and idicies of modulation, in each case you can calculate what distribution to expect. While it is tempting and probably easiest to use a DDS style generator, I recommend a synthesized one instead, to avoid trouble with numeric spurs. The HP3336 with its outstanding level-control is a much overlooked bargain for this kind of stuff. Poul-Henning -- Poul-Henning Kamp | UNIX since Zilog Zeus 3.20 phk@FreeBSD.ORG | TCP/IP since RFC 956 FreeBSD committer | BSD since 4.3-tahoe Never attribute to malice what can adequately be explained by incompetence.

BK

Bob kb8tq

Wed, Nov 29, 2017 9:52 PM

Hi

The “simple / easy / quick” approach is a pps generated by source with a small frequency
offset. If your objective is 5 ps, both your reference and your offset source will need to do
better than that. While that sounds like it’s specific to this technique, it’s actually a more
general constraint.

Just how hard this is depends a bit on your definition of jitter. Since you are looking at 1 second,
ADEV with a tau = 1 second might be a reasonable measure. If it is, then you need two sources
that are well below 5x10^-12 at one second. That eliminates most signal generators and many
atomic standards. This gets you to using things like Masers or some pretty good OCXO’s. Tuning
a Maser for a low offset is doable. Tuning an OCXO … maybe not so much.

Bob

On Nov 29, 2017, at 4:24 PM, Leo Bodnar leo@leobodnar.com wrote:

I am looking for an established and widely accepted procedure for verifying performance of high resolution time counters.

I have designed a time stamping counter for qualifying 1PPS signal performance against external reference (e.g. 10MHz master clock.)

Simple design verification check I am doing at the moment is gating random selection of master clock edges back into device's signal input and letting the device measure this test signal offset against its reference clock - which, for ideal design, should result in zero offset (modulo 100ns.) My results are roughly in line with what I expect to see http://leobodnar.com/balloons/NTP/time-sampler-test1.png

Now, what would be recognised procedure for sweeping external input pulse delay over few hundred ns in a controlled, measurable and repeatable way?

I can see few naïve approaches:

Using selectively gated (or divided) reference clock followed by adjustable delay line. E.g. something like mechanically adjusted delay lines used in HP test sets. Or, perhaps, calibrated rigid coax sections?
Slightly offset another master clock (e.g. second Rb oscillator) gated in a similar way but without delay line, followed by statistical data analysis
Trusted pulse generator with high resolution delay adjustment fed from the same master clock as the counter

I am looking for something with ~10ps accuracy, 100ns+ range, and reasonably low jitter (~5ps or better.)
It is possible that the range needs to be split up (e.g. fixed rigid coax delay line followed by a mechanically adjust section.)

This is a low budget fun project so something simple and common sense is preferred to "price on application" NIST traceable equipment.

Thanks!
Leo

time-nuts mailing list -- time-nuts@febo.com
To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts
and follow the instructions there.

Hi The “simple / easy / quick” approach is a pps generated by source with a small frequency offset. If your objective is 5 ps, both your reference and your offset source will need to do better than that. While that sounds like it’s specific to this technique, it’s actually a more general constraint. Just how hard this is depends a bit on your definition of jitter. Since you are looking at 1 second, ADEV with a tau = 1 second *might* be a reasonable measure. If it is, then you need two sources that are well below 5x10^-12 at one second. That eliminates most signal generators and many atomic standards. This gets you to using things like Masers or some pretty good OCXO’s. Tuning a Maser for a low offset is doable. Tuning an OCXO … maybe not so much. Bob > On Nov 29, 2017, at 4:24 PM, Leo Bodnar <leo@leobodnar.com> wrote: > > I am looking for an established and widely accepted procedure for verifying performance of high resolution time counters. > > I have designed a time stamping counter for qualifying 1PPS signal performance against external reference (e.g. 10MHz master clock.) > > Simple design verification check I am doing at the moment is gating random selection of master clock edges back into device's signal input and letting the device measure this test signal offset against its reference clock - which, for ideal design, should result in zero offset (modulo 100ns.) My results are roughly in line with what I expect to see http://leobodnar.com/balloons/NTP/time-sampler-test1.png > > Now, what would be recognised procedure for sweeping external input pulse delay over few hundred ns in a controlled, measurable and repeatable way? > > I can see few naïve approaches: > 1) Using selectively gated (or divided) reference clock followed by adjustable delay line. E.g. something like mechanically adjusted delay lines used in HP test sets. Or, perhaps, calibrated rigid coax sections? > 2) Slightly offset another master clock (e.g. second Rb oscillator) gated in a similar way but without delay line, followed by statistical data analysis > 3) Trusted pulse generator with high resolution delay adjustment fed from the same master clock as the counter > > I am looking for something with ~10ps accuracy, 100ns+ range, and reasonably low jitter (~5ps or better.) > It is possible that the range needs to be split up (e.g. fixed rigid coax delay line followed by a mechanically adjust section.) > > This is a low budget fun project so something simple and common sense is preferred to "price on application" NIST traceable equipment. > > Thanks! > Leo > _______________________________________________ > time-nuts mailing list -- time-nuts@febo.com > To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts > and follow the instructions there.

AZ

Andy ZL3AG

Wed, Nov 29, 2017 10:16 PM

HP 5359A Time Synthesiser?

On 30/11/2017, at 10:24 AM, Leo Bodnar wrote:

I am looking for an established and widely accepted procedure for verifying performance of high resolution time counters.

I have designed a time stamping counter for qualifying 1PPS signal performance against external reference (e.g. 10MHz master clock.)

Simple design verification check I am doing at the moment is gating random selection of master clock edges back into device's signal input and letting the device measure this test signal offset against its reference clock - which, for ideal design, should result in zero offset (modulo 100ns.) My results are roughly in line with what I expect to see http://leobodnar.com/balloons/NTP/time-sampler-test1.png

Now, what would be recognised procedure for sweeping external input pulse delay over few hundred ns in a controlled, measurable and repeatable way?

I can see few naïve approaches:

Using selectively gated (or divided) reference clock followed by adjustable delay line. E.g. something like mechanically adjusted delay lines used in HP test sets. Or, perhaps, calibrated rigid coax sections?
Slightly offset another master clock (e.g. second Rb oscillator) gated in a similar way but without delay line, followed by statistical data analysis
Trusted pulse generator with high resolution delay adjustment fed from the same master clock as the counter

I am looking for something with ~10ps accuracy, 100ns+ range, and reasonably low jitter (~5ps or better.)
It is possible that the range needs to be split up (e.g. fixed rigid coax delay line followed by a mechanically adjust section.)

This is a low budget fun project so something simple and common sense is preferred to "price on application" NIST traceable equipment.

Thanks!
Leo

time-nuts mailing list -- time-nuts@febo.com
To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts
and follow the instructions there.

HP 5359A Time Synthesiser? On 30/11/2017, at 10:24 AM, Leo Bodnar wrote: > I am looking for an established and widely accepted procedure for verifying performance of high resolution time counters. > > I have designed a time stamping counter for qualifying 1PPS signal performance against external reference (e.g. 10MHz master clock.) > > Simple design verification check I am doing at the moment is gating random selection of master clock edges back into device's signal input and letting the device measure this test signal offset against its reference clock - which, for ideal design, should result in zero offset (modulo 100ns.) My results are roughly in line with what I expect to see http://leobodnar.com/balloons/NTP/time-sampler-test1.png > > Now, what would be recognised procedure for sweeping external input pulse delay over few hundred ns in a controlled, measurable and repeatable way? > > I can see few naïve approaches: > 1) Using selectively gated (or divided) reference clock followed by adjustable delay line. E.g. something like mechanically adjusted delay lines used in HP test sets. Or, perhaps, calibrated rigid coax sections? > 2) Slightly offset another master clock (e.g. second Rb oscillator) gated in a similar way but without delay line, followed by statistical data analysis > 3) Trusted pulse generator with high resolution delay adjustment fed from the same master clock as the counter > > I am looking for something with ~10ps accuracy, 100ns+ range, and reasonably low jitter (~5ps or better.) > It is possible that the range needs to be split up (e.g. fixed rigid coax delay line followed by a mechanically adjust section.) > > This is a low budget fun project so something simple and common sense is preferred to "price on application" NIST traceable equipment. > > Thanks! > Leo > _______________________________________________ > time-nuts mailing list -- time-nuts@febo.com > To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts > and follow the instructions there.

BK

Bob kb8tq

Wed, Nov 29, 2017 10:20 PM

Hi

On Nov 29, 2017, at 5:16 PM, Andy ZL3AG via time-nuts time-nuts@febo.com wrote:

HP 5359A Time Synthesiser?

100 to 200 ps jitter …. he’s after <5 ps

Bob

On 30/11/2017, at 10:24 AM, Leo Bodnar wrote:

I am looking for an established and widely accepted procedure for verifying performance of high resolution time counters.

I have designed a time stamping counter for qualifying 1PPS signal performance against external reference (e.g. 10MHz master clock.)

Simple design verification check I am doing at the moment is gating random selection of master clock edges back into device's signal input and letting the device measure this test signal offset against its reference clock - which, for ideal design, should result in zero offset (modulo 100ns.) My results are roughly in line with what I expect to see http://leobodnar.com/balloons/NTP/time-sampler-test1.png

Now, what would be recognised procedure for sweeping external input pulse delay over few hundred ns in a controlled, measurable and repeatable way?

I can see few naïve approaches:

Using selectively gated (or divided) reference clock followed by adjustable delay line. E.g. something like mechanically adjusted delay lines used in HP test sets. Or, perhaps, calibrated rigid coax sections?
Slightly offset another master clock (e.g. second Rb oscillator) gated in a similar way but without delay line, followed by statistical data analysis
Trusted pulse generator with high resolution delay adjustment fed from the same master clock as the counter

I am looking for something with ~10ps accuracy, 100ns+ range, and reasonably low jitter (~5ps or better.)
It is possible that the range needs to be split up (e.g. fixed rigid coax delay line followed by a mechanically adjust section.)

This is a low budget fun project so something simple and common sense is preferred to "price on application" NIST traceable equipment.

Thanks!
Leo

time-nuts mailing list -- time-nuts@febo.com
To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts
and follow the instructions there.

Hi > On Nov 29, 2017, at 5:16 PM, Andy ZL3AG via time-nuts <time-nuts@febo.com> wrote: > > > HP 5359A Time Synthesiser? 100 to 200 ps jitter …. he’s after <5 ps Bob > > > On 30/11/2017, at 10:24 AM, Leo Bodnar wrote: > >> I am looking for an established and widely accepted procedure for verifying performance of high resolution time counters. >> >> I have designed a time stamping counter for qualifying 1PPS signal performance against external reference (e.g. 10MHz master clock.) >> >> Simple design verification check I am doing at the moment is gating random selection of master clock edges back into device's signal input and letting the device measure this test signal offset against its reference clock - which, for ideal design, should result in zero offset (modulo 100ns.) My results are roughly in line with what I expect to see http://leobodnar.com/balloons/NTP/time-sampler-test1.png >> >> Now, what would be recognised procedure for sweeping external input pulse delay over few hundred ns in a controlled, measurable and repeatable way? >> >> I can see few naïve approaches: >> 1) Using selectively gated (or divided) reference clock followed by adjustable delay line. E.g. something like mechanically adjusted delay lines used in HP test sets. Or, perhaps, calibrated rigid coax sections? >> 2) Slightly offset another master clock (e.g. second Rb oscillator) gated in a similar way but without delay line, followed by statistical data analysis >> 3) Trusted pulse generator with high resolution delay adjustment fed from the same master clock as the counter >> >> I am looking for something with ~10ps accuracy, 100ns+ range, and reasonably low jitter (~5ps or better.) >> It is possible that the range needs to be split up (e.g. fixed rigid coax delay line followed by a mechanically adjust section.) >> >> This is a low budget fun project so something simple and common sense is preferred to "price on application" NIST traceable equipment. >> >> Thanks! >> Leo >> _______________________________________________ >> time-nuts mailing list -- time-nuts@febo.com >> To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts >> and follow the instructions there. > > _______________________________________________ > time-nuts mailing list -- time-nuts@febo.com > To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts > and follow the instructions there.

PK

Poul-Henning Kamp

Wed, Nov 29, 2017 10:21 PM

In message F413435C-C5A8-4CC4-9912-2AC7E7662BCE@radioengineering.com, Andy ZL3AG via time-nuts writes:

HP 5359A Time Synthesiser?

If we're only talking 1PPS timestamping and nothing better and more
flexible is available, then yes.

--
Poul-Henning Kamp | UNIX since Zilog Zeus 3.20
phk@FreeBSD.ORG | TCP/IP since RFC 956
FreeBSD committer | BSD since 4.3-tahoe
Never attribute to malice what can adequately be explained by incompetence.

-------- In message <F413435C-C5A8-4CC4-9912-2AC7E7662BCE@radioengineering.com>, Andy ZL3AG via time-nuts writes: >HP 5359A Time Synthesiser? If we're only talking 1PPS timestamping and nothing better and more flexible is available, then yes. -- Poul-Henning Kamp | UNIX since Zilog Zeus 3.20 phk@FreeBSD.ORG | TCP/IP since RFC 956 FreeBSD committer | BSD since 4.3-tahoe Never attribute to malice what can adequately be explained by incompetence.

CC

Chris Caudle

Wed, Nov 29, 2017 10:47 PM

On Wed, November 29, 2017 3:51 pm, Poul-Henning Kamp wrote:

While it is tempting and probably easiest to use a DDS style
generator, I recommend a synthesized one instead, to avoid
trouble with numeric spurs.

Can you describe the distinction you are making between a synthesized
generator, and a direct-digital synthesized generator? I do not
understand what would be meant by a synthesizer which is not DDS.

The HP3336 with its outstanding level-control is a much
overlooked bargain for this kind of stuff.

I looked for the manual, and it seems to have ROM feeding values to a DAC.
Is that not DDS?

--
Chris Caudle

On Wed, November 29, 2017 3:51 pm, Poul-Henning Kamp wrote: > While it is tempting and probably easiest to use a DDS style > generator, I recommend a synthesized one instead, to avoid > trouble with numeric spurs. Can you describe the distinction you are making between a synthesized generator, and a direct-digital synthesized generator? I do not understand what would be meant by a synthesizer which is not DDS. > The HP3336 with its outstanding level-control is a much > overlooked bargain for this kind of stuff. I looked for the manual, and it seems to have ROM feeding values to a DAC. Is that not DDS? -- Chris Caudle

BK

Bob kb8tq

Wed, Nov 29, 2017 10:56 PM

Hi

There are a number of ways to build a synthesizer that do not involve a modern
DDS architecture. The gotcha with a DDS in this case are the sawtooth spurs. To
get them down to the 5 ps level, you would need a DDS with a clock that is well into
the 100’s of GHz.

Bob

On Nov 29, 2017, at 5:47 PM, Chris Caudle chris@chriscaudle.org wrote:

On Wed, November 29, 2017 3:51 pm, Poul-Henning Kamp wrote:

While it is tempting and probably easiest to use a DDS style
generator, I recommend a synthesized one instead, to avoid
trouble with numeric spurs.

Can you describe the distinction you are making between a synthesized
generator, and a direct-digital synthesized generator? I do not
understand what would be meant by a synthesizer which is not DDS.

The HP3336 with its outstanding level-control is a much
overlooked bargain for this kind of stuff.

I looked for the manual, and it seems to have ROM feeding values to a DAC.
Is that not DDS?

--
Chris Caudle

time-nuts mailing list -- time-nuts@febo.com
To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts
and follow the instructions there.

Hi There are a number of ways to build a synthesizer that do not involve a modern DDS architecture. The gotcha with a DDS in this case are the sawtooth spurs. To get them down to the 5 ps level, you would need a DDS with a clock that is well into the 100’s of GHz. Bob > On Nov 29, 2017, at 5:47 PM, Chris Caudle <chris@chriscaudle.org> wrote: > > On Wed, November 29, 2017 3:51 pm, Poul-Henning Kamp wrote: >> While it is tempting and probably easiest to use a DDS style >> generator, I recommend a synthesized one instead, to avoid >> trouble with numeric spurs. > > Can you describe the distinction you are making between a synthesized > generator, and a direct-digital synthesized generator? I do not > understand what would be meant by a synthesizer which is not DDS. > >> The HP3336 with its outstanding level-control is a much >> overlooked bargain for this kind of stuff. > > I looked for the manual, and it seems to have ROM feeding values to a DAC. > Is that not DDS? > > -- > Chris Caudle > > > _______________________________________________ > time-nuts mailing list -- time-nuts@febo.com > To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts > and follow the instructions there.

PK

Poul-Henning Kamp

Wed, Nov 29, 2017 11:17 PM

In message 5e3f68620fdb8f2e5d62e9907a44c6eb.squirrel@email.powweb.com, "Chris Caudle" writes:

On Wed, November 29, 2017 3:51 pm, Poul-Henning Kamp wrote:

While it is tempting and probably easiest to use a DDS style
generator, I recommend a synthesized one instead, to avoid
trouble with numeric spurs.

Can you describe the distinction you are making between a synthesized
generator, and a direct-digital synthesized generator? I do not
understand what would be meant by a synthesizer which is not DDS.

What used to be called a "Synthesized Signal Generator" was a almost
or even entirely analog beast, which means almost all distortion is
harmonic (2f, 3f, 4f, ...)

This is a good place to start, in particular the App-note at the
bottom:

http://hpmemoryproject.org/news/5100/hp5100_page_00.htm

DDS is "Direct Digital Synthesis" where you basically generate the
desired signal with a computer and D/A converter. Because this
discrete rather than continuous in time, there are all sorts of
"weird" distortion products, and aliasing artifacts.

--
Poul-Henning Kamp | UNIX since Zilog Zeus 3.20
phk@FreeBSD.ORG | TCP/IP since RFC 956
FreeBSD committer | BSD since 4.3-tahoe
Never attribute to malice what can adequately be explained by incompetence.

-------- In message <5e3f68620fdb8f2e5d62e9907a44c6eb.squirrel@email.powweb.com>, "Chris Caudle" writes: >On Wed, November 29, 2017 3:51 pm, Poul-Henning Kamp wrote: >> While it is tempting and probably easiest to use a DDS style >> generator, I recommend a synthesized one instead, to avoid >> trouble with numeric spurs. > >Can you describe the distinction you are making between a synthesized >generator, and a direct-digital synthesized generator? I do not >understand what would be meant by a synthesizer which is not DDS. What used to be called a "Synthesized Signal Generator" was a almost or even entirely analog beast, which means almost all distortion is harmonic (2f, 3f, 4f, ...) This is a good place to start, in particular the App-note at the bottom: http://hpmemoryproject.org/news/5100/hp5100_page_00.htm DDS is "Direct Digital Synthesis" where you basically generate the desired signal with a computer and D/A converter. Because this discrete rather than continuous in time, there are all sorts of "weird" distortion products, and aliasing artifacts. -- Poul-Henning Kamp | UNIX since Zilog Zeus 3.20 phk@FreeBSD.ORG | TCP/IP since RFC 956 FreeBSD committer | BSD since 4.3-tahoe Never attribute to malice what can adequately be explained by incompetence.

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