Hi

This gets into the “other side” of the whole comparator / squaring circuit test process.
What matters for ADEV and what matters for phase noise at 100KHz offset likely are
not the same thing. A lot of circuits do quite well inside 100 Hz, but not so well above
that offset.

Driving a 5V powered CMOS gate with 5.5V p-p does a pretty good job ….

Bob

On Wed, 4 Oct 2017 11:01:31 -0400
Bob kb8tq kb8tq@n1k.org wrote:

Yes. Definitely something one should consider.

For completeness:

• For cycle-to-cycle jitter what matters is the white noise floor.
  Ie everything above 100Hz-1kHz, as this is the largest contributor
  of "short" tau jitter. This is the component that limits e.g. the
  single shot resolution of time-interval counters.

• For ADEV/TDEV at "long" taus >1-100s what matters is the close-in, 1/f^a,
  flicker noise. As white noise averages out with sqrt(n), with n
  being the number of samples taken, but 1/f^a noise does not.

When the transistion to from short to long taus happens depends as much
on the noise as on the rate of measurement. If we measure a 1PPS, the
the ADEV at tau=1s will be dominated by white noise and at tau=10s it
could be still a significant portion of the noise seen. On the other
hand, if we measure a 1kHz signal (at that rate), the tau=1s will be
(most likely) dominated by the flicker noise.

If you have this much signal, yes. Not everyone has the luxury of an
steady +19dBm input signal. Part of the reason why I am looking into
this is because I wanted a squaring circuit that can work down to +2dBm,
where, so I have been told, CMOS gates do not work well anymore.

		Attila Kinali

--
It is upon moral qualities that a society is ultimately founded. All
the prosperity and technological sophistication in the world is of no
use without that foundation.
-- Miss Matheson, The Diamond Age, Neil Stephenson

Hi

You don’t need 19 DBM to put 5.5V into a gate. A broadband transformer
or a matching network and 0 DBM will do just fine. Neither one is terribly
hard to come by. Neither one takes up much board space.

Bob

On Wed, 4 Oct 2017 16:47:22 -0400
Bob kb8tq kb8tq@n1k.org wrote:

Right.. given that CMOS gates have a very high input impedance,
this works. The only thing that needs to be done is proper limiting
of the signal in order not to destroy the gate (ie two Schottky diodes).

		Attila Kinali

--
It is upon moral qualities that a society is ultimately founded. All
the prosperity and technological sophistication in the world is of no
use without that foundation.
-- Miss Matheson, The Diamond Age, Neil Stephenson

Hello,

I think that the important point about sine-to-square converter is about
how you measure the phase noise.
If you use such converter, you don't care about the signal noise when the
output is clipped. But phase noise analyzers care about that too.
That's why Linear characterized LTC6957 additive phase noise using the REF
input port of phase noise analyzer. That port is connected to the LO input
of the internal mixer, therefore it cares only rising/falling edges.
And the worst thing is that push-pull CMOS stage are not operated in
high-gain, so no PSRR.

Ie everything above 100Hz-1kHz, as this is the largest contributor
of "short" tau jitter. This is the component that limits e.g. the
single shot resolution of time-interval counters.

Not to be pedantic, but time-interval counters are sensitive to something
similar to period jitter, i.e. if phi(t) is the random phase fluctuation,
then they are sensible to phi(t+T)-phi(t), where T is the measurement time.
Period jitter has the same definition, but the "T" is the nominal period of
the clock signal. Indeed, the phase noise contribution starts to be
relevant above kHz.

cheers,
Mattia

2017-10-04 18:49 GMT+02:00 Attila Kinali attila@kinali.ch: