Empathy List Archives

JL

Joakim Langlet

Wed, Aug 10, 2016 9:30 PM

Dear time-nuts,

My name is Joakim Langlet (SM0OET) and I just recently joined this list.
As Brooks Shera was mentioned, I remembered that I was referenced in the
footnotes of the original article in the QST - July 1998. It feels
almost historical now. Brooks bought a few OCXOs from me.

I am currently working on a GPS stabilized OCXO.
It is based on a Xilinx Zynq FPGA as the processor and counter arrangement.
The hardware is starting to take shape. The control voltage of a 20 MHz
OCXO is set by a DAC coupling from which I hope to set the voltage in
very small steps.
The OCXO has a CMOS level output which is converted to LVDS and is wired
to the FPGA board. The Xilinx Zynq take a minimum frequency of 19 MHz as
input to the PLL of the clock tile. My intention is to scale up the
clock to some where a bit over 200 MHz to be fed to the counters.The 1
PPS from the GPS receiver is also fed into the FPGA to gate the counters.

The reason for my choice of processor is that I want to run Linux on it
in order benefit from the large software base. Time distribution using
PTPv2 and a nice web-application to visualize and control what is going
on inside is part of the intended concept.

I still have a long way to the finish line but I will try to present
some results as I proceed.

I am following what is written on this list with great interest. It
feels good to know that I am not the only nut ....

BR/
Joakim

Dear time-nuts, My name is Joakim Langlet (SM0OET) and I just recently joined this list. As Brooks Shera was mentioned, I remembered that I was referenced in the footnotes of the original article in the QST - July 1998. It feels almost historical now. Brooks bought a few OCXOs from me. I am currently working on a GPS stabilized OCXO. It is based on a Xilinx Zynq FPGA as the processor and counter arrangement. The hardware is starting to take shape. The control voltage of a 20 MHz OCXO is set by a DAC coupling from which I hope to set the voltage in very small steps. The OCXO has a CMOS level output which is converted to LVDS and is wired to the FPGA board. The Xilinx Zynq take a minimum frequency of 19 MHz as input to the PLL of the clock tile. My intention is to scale up the clock to some where a bit over 200 MHz to be fed to the counters.The 1 PPS from the GPS receiver is also fed into the FPGA to gate the counters. The reason for my choice of processor is that I want to run Linux on it in order benefit from the large software base. Time distribution using PTPv2 and a nice web-application to visualize and control what is going on inside is part of the intended concept. I still have a long way to the finish line but I will try to present some results as I proceed. I am following what is written on this list with great interest. It feels good to know that I am not the only nut .... BR/ Joakim

CA

Chris Albertson

Thu, Aug 11, 2016 3:18 AM

Thanks for pointing out the Zynq. Wow you get a dual core ARM and an
FPGA all in one package. It seems overkill for a GPSDO but not the
type you are making as you can transferring the time out of the GPSDO
using PTP.

The Zyng looks to the the perfect platform for low-cost SDR.

On Wed, Aug 10, 2016 at 2:30 PM, Joakim Langlet
joakim.langlet@seaview.se wrote:

Dear time-nuts,

My name is Joakim Langlet (SM0OET) and I just recently joined this list. As
Brooks Shera was mentioned, I remembered that I was referenced in the
footnotes of the original article in the QST - July 1998. It feels almost
historical now. Brooks bought a few OCXOs from me.

I am currently working on a GPS stabilized OCXO.
It is based on a Xilinx Zynq FPGA as the processor and counter arrangement.
The hardware is starting to take shape. The control voltage of a 20 MHz OCXO
is set by a DAC coupling from which I hope to set the voltage in very small
steps.
The OCXO has a CMOS level output which is converted to LVDS and is wired to
the FPGA board. The Xilinx Zynq take a minimum frequency of 19 MHz as input
to the PLL of the clock tile. My intention is to scale up the clock to some
where a bit over 200 MHz to be fed to the counters.The 1 PPS from the GPS
receiver is also fed into the FPGA to gate the counters.

The reason for my choice of processor is that I want to run Linux on it in
order benefit from the large software base. Time distribution using PTPv2
and a nice web-application to visualize and control what is going on inside
is part of the intended concept.

I still have a long way to the finish line but I will try to present some
results as I proceed.

I am following what is written on this list with great interest. It feels
good to know that I am not the only nut ....

BR/
Joakim

time-nuts mailing list -- time-nuts@febo.com
To unsubscribe, go to
https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts
and follow the instructions there.

--

Chris Albertson
Redondo Beach, California

Thanks for pointing out the Zynq. Wow you get a dual core ARM and an FPGA all in one package. It seems overkill for a GPSDO but not the type you are making as you can transferring the time out of the GPSDO using PTP. The Zyng looks to the the perfect platform for low-cost SDR. On Wed, Aug 10, 2016 at 2:30 PM, Joakim Langlet <joakim.langlet@seaview.se> wrote: > Dear time-nuts, > > My name is Joakim Langlet (SM0OET) and I just recently joined this list. As > Brooks Shera was mentioned, I remembered that I was referenced in the > footnotes of the original article in the QST - July 1998. It feels almost > historical now. Brooks bought a few OCXOs from me. > > I am currently working on a GPS stabilized OCXO. > It is based on a Xilinx Zynq FPGA as the processor and counter arrangement. > The hardware is starting to take shape. The control voltage of a 20 MHz OCXO > is set by a DAC coupling from which I hope to set the voltage in very small > steps. > The OCXO has a CMOS level output which is converted to LVDS and is wired to > the FPGA board. The Xilinx Zynq take a minimum frequency of 19 MHz as input > to the PLL of the clock tile. My intention is to scale up the clock to some > where a bit over 200 MHz to be fed to the counters.The 1 PPS from the GPS > receiver is also fed into the FPGA to gate the counters. > > The reason for my choice of processor is that I want to run Linux on it in > order benefit from the large software base. Time distribution using PTPv2 > and a nice web-application to visualize and control what is going on inside > is part of the intended concept. > > I still have a long way to the finish line but I will try to present some > results as I proceed. > > I am following what is written on this list with great interest. It feels > good to know that I am not the only nut .... > > BR/ > Joakim > _______________________________________________ > time-nuts mailing list -- time-nuts@febo.com > To unsubscribe, go to > https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts > and follow the instructions there. -- Chris Albertson Redondo Beach, California

MW

Michael Wouters

Thu, Aug 11, 2016 8:03 AM

The Red Pitaya uses a Zynq, and there's an (unofficial) SDR application
available to experiment with.

Cheers
Michael
On Thursday, 11 August 2016, Chris Albertson albertson.chris@gmail.com
wrote:

Thanks for pointing out the Zynq. Wow you get a dual core ARM and an
FPGA all in one package. It seems overkill for a GPSDO but not the
type you are making as you can transferring the time out of the GPSDO
using PTP.

The Zyng looks to the the perfect platform for low-cost SDR.

On Wed, Aug 10, 2016 at 2:30 PM, Joakim Langlet
<joakim.langlet@seaview.se javascript:;> wrote:

Dear time-nuts,

My name is Joakim Langlet (SM0OET) and I just recently joined this list.

As

Brooks Shera was mentioned, I remembered that I was referenced in the
footnotes of the original article in the QST - July 1998. It feels almost
historical now. Brooks bought a few OCXOs from me.

I am currently working on a GPS stabilized OCXO.
It is based on a Xilinx Zynq FPGA as the processor and counter

arrangement.

The hardware is starting to take shape. The control voltage of a 20 MHz

OCXO

is set by a DAC coupling from which I hope to set the voltage in very

small

steps.
The OCXO has a CMOS level output which is converted to LVDS and is wired

to

the FPGA board. The Xilinx Zynq take a minimum frequency of 19 MHz as

input

to the PLL of the clock tile. My intention is to scale up the clock to

some

where a bit over 200 MHz to be fed to the counters.The 1 PPS from the GPS
receiver is also fed into the FPGA to gate the counters.

The reason for my choice of processor is that I want to run Linux on it

in

order benefit from the large software base. Time distribution using PTPv2
and a nice web-application to visualize and control what is going on

inside

is part of the intended concept.

I still have a long way to the finish line but I will try to present some
results as I proceed.

I am following what is written on this list with great interest. It feels
good to know that I am not the only nut ....

BR/
Joakim

time-nuts mailing list -- time-nuts@febo.com javascript:;
To unsubscribe, go to
https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts
and follow the instructions there.

--

Chris Albertson
Redondo Beach, California

time-nuts mailing list -- time-nuts@febo.com javascript:;
To unsubscribe, go to https://www.febo.com/cgi-bin/
mailman/listinfo/time-nuts
and follow the instructions there.

The Red Pitaya uses a Zynq, and there's an (unofficial) SDR application available to experiment with. Cheers Michael On Thursday, 11 August 2016, Chris Albertson <albertson.chris@gmail.com> wrote: > Thanks for pointing out the Zynq. Wow you get a dual core ARM and an > FPGA all in one package. It seems overkill for a GPSDO but not the > type you are making as you can transferring the time out of the GPSDO > using PTP. > > The Zyng looks to the the perfect platform for low-cost SDR. > > On Wed, Aug 10, 2016 at 2:30 PM, Joakim Langlet > <joakim.langlet@seaview.se <javascript:;>> wrote: > > Dear time-nuts, > > > > My name is Joakim Langlet (SM0OET) and I just recently joined this list. > As > > Brooks Shera was mentioned, I remembered that I was referenced in the > > footnotes of the original article in the QST - July 1998. It feels almost > > historical now. Brooks bought a few OCXOs from me. > > > > I am currently working on a GPS stabilized OCXO. > > It is based on a Xilinx Zynq FPGA as the processor and counter > arrangement. > > The hardware is starting to take shape. The control voltage of a 20 MHz > OCXO > > is set by a DAC coupling from which I hope to set the voltage in very > small > > steps. > > The OCXO has a CMOS level output which is converted to LVDS and is wired > to > > the FPGA board. The Xilinx Zynq take a minimum frequency of 19 MHz as > input > > to the PLL of the clock tile. My intention is to scale up the clock to > some > > where a bit over 200 MHz to be fed to the counters.The 1 PPS from the GPS > > receiver is also fed into the FPGA to gate the counters. > > > > The reason for my choice of processor is that I want to run Linux on it > in > > order benefit from the large software base. Time distribution using PTPv2 > > and a nice web-application to visualize and control what is going on > inside > > is part of the intended concept. > > > > I still have a long way to the finish line but I will try to present some > > results as I proceed. > > > > I am following what is written on this list with great interest. It feels > > good to know that I am not the only nut .... > > > > BR/ > > Joakim > > _______________________________________________ > > time-nuts mailing list -- time-nuts@febo.com <javascript:;> > > To unsubscribe, go to > > https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts > > and follow the instructions there. > > > > -- > > Chris Albertson > Redondo Beach, California > _______________________________________________ > time-nuts mailing list -- time-nuts@febo.com <javascript:;> > To unsubscribe, go to https://www.febo.com/cgi-bin/ > mailman/listinfo/time-nuts > and follow the instructions there. >

JL

Joakim Langlet

Thu, Aug 11, 2016 10:03 AM

You are so right, Chris.
The Zynq is absolutely an overkill for an ordinary GPSDO.
What I think is attractive with the Zynq are the possibilities to
experiment with different implementations of counters and gates without
soldering and that you can get pretty fast counters well integrated with
the processor.

The Zynq would be pretty good for SDR experiments too, as you point out.
That may well be my next project.

On 2016-08-11 05:18, Chris Albertson wrote:

Thanks for pointing out the Zynq. Wow you get a dual core ARM and an
FPGA all in one package. It seems overkill for a GPSDO but not the
type you are making as you can transferring the time out of the GPSDO
using PTP.

The Zyng looks to the the perfect platform for low-cost SDR.

You are so right, Chris. The Zynq is absolutely an overkill for an ordinary GPSDO. What I think is attractive with the Zynq are the possibilities to experiment with different implementations of counters and gates without soldering and that you can get pretty fast counters well integrated with the processor. The Zynq would be pretty good for SDR experiments too, as you point out. That may well be my next project. On 2016-08-11 05:18, Chris Albertson wrote: > Thanks for pointing out the Zynq. Wow you get a dual core ARM and an > FPGA all in one package. It seems overkill for a GPSDO but not the > type you are making as you can transferring the time out of the GPSDO > using PTP. > > The Zyng looks to the the perfect platform for low-cost SDR.

BC

Bob Camp

Thu, Aug 11, 2016 11:06 AM

Hi

To your earlier point, there are a number of fairly low cost boards with Zynq’s on them.
They aren’t into the $5 range, but they are not that much more than one of the Beagle
boards.

Bob

On Aug 10, 2016, at 11:18 PM, Chris Albertson albertson.chris@gmail.com wrote:

Thanks for pointing out the Zynq. Wow you get a dual core ARM and an
FPGA all in one package. It seems overkill for a GPSDO but not the
type you are making as you can transferring the time out of the GPSDO
using PTP.

The Zyng looks to the the perfect platform for low-cost SDR.

On Wed, Aug 10, 2016 at 2:30 PM, Joakim Langlet
joakim.langlet@seaview.se wrote:

Dear time-nuts,

My name is Joakim Langlet (SM0OET) and I just recently joined this list. As
Brooks Shera was mentioned, I remembered that I was referenced in the
footnotes of the original article in the QST - July 1998. It feels almost
historical now. Brooks bought a few OCXOs from me.

I am currently working on a GPS stabilized OCXO.
It is based on a Xilinx Zynq FPGA as the processor and counter arrangement.
The hardware is starting to take shape. The control voltage of a 20 MHz OCXO
is set by a DAC coupling from which I hope to set the voltage in very small
steps.
The OCXO has a CMOS level output which is converted to LVDS and is wired to
the FPGA board. The Xilinx Zynq take a minimum frequency of 19 MHz as input
to the PLL of the clock tile. My intention is to scale up the clock to some
where a bit over 200 MHz to be fed to the counters.The 1 PPS from the GPS
receiver is also fed into the FPGA to gate the counters.

The reason for my choice of processor is that I want to run Linux on it in
order benefit from the large software base. Time distribution using PTPv2
and a nice web-application to visualize and control what is going on inside
is part of the intended concept.

I still have a long way to the finish line but I will try to present some
results as I proceed.

I am following what is written on this list with great interest. It feels
good to know that I am not the only nut ....

BR/
Joakim

time-nuts mailing list -- time-nuts@febo.com
To unsubscribe, go to
https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts
and follow the instructions there.

--

Chris Albertson
Redondo Beach, California

time-nuts mailing list -- time-nuts@febo.com
To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts
and follow the instructions there.

Hi To your earlier point, there are a number of fairly low cost boards with Zynq’s on them. They aren’t into the $5 range, but they are not that much more than one of the Beagle boards. Bob > On Aug 10, 2016, at 11:18 PM, Chris Albertson <albertson.chris@gmail.com> wrote: > > Thanks for pointing out the Zynq. Wow you get a dual core ARM and an > FPGA all in one package. It seems overkill for a GPSDO but not the > type you are making as you can transferring the time out of the GPSDO > using PTP. > > The Zyng looks to the the perfect platform for low-cost SDR. > > On Wed, Aug 10, 2016 at 2:30 PM, Joakim Langlet > <joakim.langlet@seaview.se> wrote: >> Dear time-nuts, >> >> My name is Joakim Langlet (SM0OET) and I just recently joined this list. As >> Brooks Shera was mentioned, I remembered that I was referenced in the >> footnotes of the original article in the QST - July 1998. It feels almost >> historical now. Brooks bought a few OCXOs from me. >> >> I am currently working on a GPS stabilized OCXO. >> It is based on a Xilinx Zynq FPGA as the processor and counter arrangement. >> The hardware is starting to take shape. The control voltage of a 20 MHz OCXO >> is set by a DAC coupling from which I hope to set the voltage in very small >> steps. >> The OCXO has a CMOS level output which is converted to LVDS and is wired to >> the FPGA board. The Xilinx Zynq take a minimum frequency of 19 MHz as input >> to the PLL of the clock tile. My intention is to scale up the clock to some >> where a bit over 200 MHz to be fed to the counters.The 1 PPS from the GPS >> receiver is also fed into the FPGA to gate the counters. >> >> The reason for my choice of processor is that I want to run Linux on it in >> order benefit from the large software base. Time distribution using PTPv2 >> and a nice web-application to visualize and control what is going on inside >> is part of the intended concept. >> >> I still have a long way to the finish line but I will try to present some >> results as I proceed. >> >> I am following what is written on this list with great interest. It feels >> good to know that I am not the only nut .... >> >> BR/ >> Joakim >> _______________________________________________ >> time-nuts mailing list -- time-nuts@febo.com >> To unsubscribe, go to >> https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts >> and follow the instructions there. > > > > -- > > Chris Albertson > Redondo Beach, California > _______________________________________________ > time-nuts mailing list -- time-nuts@febo.com > To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts > and follow the instructions there.

J

jimlux

Thu, Aug 11, 2016 11:46 AM

On 8/10/16 8:18 PM, Chris Albertson wrote:

Thanks for pointing out the Zynq. Wow you get a dual core ARM and an
FPGA all in one package. It seems overkill for a GPSDO but not the
type you are making as you can transferring the time out of the GPSDO
using PTP.

The Zyng looks to the the perfect platform for low-cost SDR.

There are SDRs based on the Zynq.

http://zedboard.org/product/zynq-sdr-ii-eval
http://www.mathworks.com/hardware-support/zynq-sdr.html
http://gnuradio.org/redmine/projects/gnuradio/wiki/Embedded

On 8/10/16 8:18 PM, Chris Albertson wrote: > Thanks for pointing out the Zynq. Wow you get a dual core ARM and an > FPGA all in one package. It seems overkill for a GPSDO but not the > type you are making as you can transferring the time out of the GPSDO > using PTP. > > The Zyng looks to the the perfect platform for low-cost SDR. There are SDRs based on the Zynq. http://zedboard.org/product/zynq-sdr-ii-eval http://www.mathworks.com/hardware-support/zynq-sdr.html http://gnuradio.org/redmine/projects/gnuradio/wiki/Embedded

B

bownes

Thu, Aug 11, 2016 3:52 PM

There are also some nice cypresses semiconductor parts that are similar and have a really nice dev environment.
Basically a core surrounded by programmable logic. Code in C ore close to it.

On Aug 11, 2016, at 07:06, Bob Camp kb8tq@n1k.org wrote:

Hi

To your earlier point, there are a number of fairly low cost boards with Zynq’s on them.
They aren’t into the $5 range, but they are not that much more than one of the Beagle
boards.

Bob

On Aug 10, 2016, at 11:18 PM, Chris Albertson albertson.chris@gmail.com wrote:

Thanks for pointing out the Zynq. Wow you get a dual core ARM and an
FPGA all in one package. It seems overkill for a GPSDO but not the
type you are making as you can transferring the time out of the GPSDO
using PTP.

The Zyng looks to the the perfect platform for low-cost SDR.

On Wed, Aug 10, 2016 at 2:30 PM, Joakim Langlet
joakim.langlet@seaview.se wrote:

Dear time-nuts,

My name is Joakim Langlet (SM0OET) and I just recently joined this list. As
Brooks Shera was mentioned, I remembered that I was referenced in the
footnotes of the original article in the QST - July 1998. It feels almost
historical now. Brooks bought a few OCXOs from me.

I am currently working on a GPS stabilized OCXO.
It is based on a Xilinx Zynq FPGA as the processor and counter arrangement.
The hardware is starting to take shape. The control voltage of a 20 MHz OCXO
is set by a DAC coupling from which I hope to set the voltage in very small
steps.
The OCXO has a CMOS level output which is converted to LVDS and is wired to
the FPGA board. The Xilinx Zynq take a minimum frequency of 19 MHz as input
to the PLL of the clock tile. My intention is to scale up the clock to some
where a bit over 200 MHz to be fed to the counters.The 1 PPS from the GPS
receiver is also fed into the FPGA to gate the counters.

The reason for my choice of processor is that I want to run Linux on it in
order benefit from the large software base. Time distribution using PTPv2
and a nice web-application to visualize and control what is going on inside
is part of the intended concept.

I still have a long way to the finish line but I will try to present some
results as I proceed.

I am following what is written on this list with great interest. It feels
good to know that I am not the only nut ....

BR/
Joakim

time-nuts mailing list -- time-nuts@febo.com
To unsubscribe, go to
https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts
and follow the instructions there.

--

Chris Albertson
Redondo Beach, California

time-nuts mailing list -- time-nuts@febo.com
To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts
and follow the instructions there.

There are also some nice cypresses semiconductor parts that are similar and have a really nice dev environment. Basically a core surrounded by programmable logic. Code in C ore close to it. > On Aug 11, 2016, at 07:06, Bob Camp <kb8tq@n1k.org> wrote: > > Hi > > To your earlier point, there are a number of fairly low cost boards with Zynq’s on them. > They aren’t into the $5 range, but they are not that much more than one of the Beagle > boards. > > Bob > > >> On Aug 10, 2016, at 11:18 PM, Chris Albertson <albertson.chris@gmail.com> wrote: >> >> Thanks for pointing out the Zynq. Wow you get a dual core ARM and an >> FPGA all in one package. It seems overkill for a GPSDO but not the >> type you are making as you can transferring the time out of the GPSDO >> using PTP. >> >> The Zyng looks to the the perfect platform for low-cost SDR. >> >> On Wed, Aug 10, 2016 at 2:30 PM, Joakim Langlet >> <joakim.langlet@seaview.se> wrote: >>> Dear time-nuts, >>> >>> My name is Joakim Langlet (SM0OET) and I just recently joined this list. As >>> Brooks Shera was mentioned, I remembered that I was referenced in the >>> footnotes of the original article in the QST - July 1998. It feels almost >>> historical now. Brooks bought a few OCXOs from me. >>> >>> I am currently working on a GPS stabilized OCXO. >>> It is based on a Xilinx Zynq FPGA as the processor and counter arrangement. >>> The hardware is starting to take shape. The control voltage of a 20 MHz OCXO >>> is set by a DAC coupling from which I hope to set the voltage in very small >>> steps. >>> The OCXO has a CMOS level output which is converted to LVDS and is wired to >>> the FPGA board. The Xilinx Zynq take a minimum frequency of 19 MHz as input >>> to the PLL of the clock tile. My intention is to scale up the clock to some >>> where a bit over 200 MHz to be fed to the counters.The 1 PPS from the GPS >>> receiver is also fed into the FPGA to gate the counters. >>> >>> The reason for my choice of processor is that I want to run Linux on it in >>> order benefit from the large software base. Time distribution using PTPv2 >>> and a nice web-application to visualize and control what is going on inside >>> is part of the intended concept. >>> >>> I still have a long way to the finish line but I will try to present some >>> results as I proceed. >>> >>> I am following what is written on this list with great interest. It feels >>> good to know that I am not the only nut .... >>> >>> BR/ >>> Joakim >>> _______________________________________________ >>> time-nuts mailing list -- time-nuts@febo.com >>> To unsubscribe, go to >>> https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts >>> and follow the instructions there. >> >> >> >> -- >> >> Chris Albertson >> Redondo Beach, California >> _______________________________________________ >> time-nuts mailing list -- time-nuts@febo.com >> To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts >> and follow the instructions there. > > _______________________________________________ > time-nuts mailing list -- time-nuts@febo.com > To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts > and follow the instructions there.

BS

Bob Stewart

Thu, Aug 11, 2016 4:01 PM

A number of posts have appeared about Zynq SDRs on the "Shera revisited" thread. So, I'd like to ask the more general question: Are there any low cost SDRs that are suitable for measuring phase noise when coupled with a DMTD? I believe what I'm looking for is something with enough bits to work in the audio range down to DC. Yes, I could use a modified sound card, but I'm really looking for something not sound card related. My thought was to use a DMTD with a heterodyne frequency of maybe 5KHz.

Bob -----------------------------------------------------------------
AE6RV.com

GFS GPSDO list:
groups.yahoo.com/neo/groups/GFS-GPSDOs/info

A number of posts have appeared about Zynq SDRs on the "Shera revisited" thread. So, I'd like to ask the more general question: Are there any low cost SDRs that are suitable for measuring phase noise when coupled with a DMTD? I believe what I'm looking for is something with enough bits to work in the audio range down to DC. Yes, I could use a modified sound card, but I'm really looking for something not sound card related. My thought was to use a DMTD with a heterodyne frequency of maybe 5KHz. Bob ----------------------------------------------------------------- AE6RV.com GFS GPSDO list: groups.yahoo.com/neo/groups/GFS-GPSDOs/info

BC

Brooke Clarke

Thu, Aug 11, 2016 6:36 PM

Hi Bob:

The SDR-IQ has a lower frequency limit of 500 Hz.
http://www.prc68.com/I/Bats.shtml#SDRIQ

There is a mod that replaces the on board 66 MHz oscillator with one locked to 10 MHz.

--
Have Fun,

Brooke Clarke, N6GCE
http://www.PRC68.com
http://www.end2partygovernment.com/2012Issues.html
The lesser of evils is still evil.

-------- Original Message --------

A number of posts have appeared about Zynq SDRs on the "Shera revisited" thread. So, I'd like to ask the more general question: Are there any low cost SDRs that are suitable for measuring phase noise when coupled with a DMTD? I believe what I'm looking for is something with enough bits to work in the audio range down to DC. Yes, I could use a modified sound card, but I'm really looking for something not sound card related. My thought was to use a DMTD with a heterodyne frequency of maybe 5KHz.

Bob -----------------------------------------------------------------
AE6RV.com

GFS GPSDO list:
groups.yahoo.com/neo/groups/GFS-GPSDOs/info

time-nuts mailing list -- time-nuts@febo.com
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Hi Bob: The SDR-IQ has a lower frequency limit of 500 Hz. http://www.prc68.com/I/Bats.shtml#SDRIQ There is a mod that replaces the on board 66 MHz oscillator with one locked to 10 MHz. -- Have Fun, Brooke Clarke, N6GCE http://www.PRC68.com http://www.end2partygovernment.com/2012Issues.html The lesser of evils is still evil. -------- Original Message -------- > A number of posts have appeared about Zynq SDRs on the "Shera revisited" thread. So, I'd like to ask the more general question: Are there any low cost SDRs that are suitable for measuring phase noise when coupled with a DMTD? I believe what I'm looking for is something with enough bits to work in the audio range down to DC. Yes, I could use a modified sound card, but I'm really looking for something not sound card related. My thought was to use a DMTD with a heterodyne frequency of maybe 5KHz. > > Bob ----------------------------------------------------------------- > AE6RV.com > > GFS GPSDO list: > groups.yahoo.com/neo/groups/GFS-GPSDOs/info > _______________________________________________ > time-nuts mailing list -- time-nuts@febo.com > To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts > and follow the instructions there. >

BS

Bob Stewart

Thu, Aug 11, 2016 7:29 PM

Hi Brooke,
It looks like I've asked a question poorly, yet again. So, let me try again. I have this idea of combining a DMTD with an SDR. So, said that way, it looks like what I really need is a 2-channel audio SDR. And having said that, maybe what I'm looking for is an external USB sound card. Those I can find. I can probably even figure out how to convert them to DC and supply them with a disciplined oscillator, if needed.

Bob
-----------------------------------------------------------------
AE6RV.com

GFS GPSDO list:
groups.yahoo.com/neo/groups/GFS-GPSDOs/info

  From: Brooke Clarke <brooke@pacific.net>

To: Discussion of precise time and frequency measurement time-nuts@febo.com
Sent: Thursday, August 11, 2016 1:36 PM
Subject: Re: [time-nuts] Low cost SDR suitable for phase noise measurement?

Hi Bob:

The SDR-IQ has a lower frequency limit of 500 Hz.
http://www.prc68.com/I/Bats.shtml#SDRIQ

There is a mod that replaces the on board 66 MHz oscillator with one locked to 10 MHz.

--
Have Fun,

Brooke Clarke, N6GCE
http://www.PRC68.com
http://www.end2partygovernment.com/2012Issues.html
The lesser of evils is still evil.

-------- Original Message --------

A number of posts have appeared about Zynq SDRs on the "Shera revisited" thread. So, I'd like to ask the more general question: Are there any low cost SDRs that are suitable for measuring phase noise when coupled with a DMTD? I believe what I'm looking for is something with enough bits to work in the audio range down to DC. Yes, I could use a modified sound card, but I'm really looking for something not sound card related. My thought was to use a DMTD with a heterodyne frequency of maybe 5KHz.

Bob -----------------------------------------------------------------
AE6RV.com

GFS GPSDO list:
groups.yahoo.com/neo/groups/GFS-GPSDOs/info

time-nuts mailing list -- time-nuts@febo.com
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Hi Brooke, It looks like I've asked a question poorly, yet again. So, let me try again. I have this idea of combining a DMTD with an SDR. So, said that way, it looks like what I really need is a 2-channel audio SDR. And having said that, maybe what I'm looking for is an external USB sound card. Those I can find. I can probably even figure out how to convert them to DC and supply them with a disciplined oscillator, if needed. Bob ----------------------------------------------------------------- AE6RV.com GFS GPSDO list: groups.yahoo.com/neo/groups/GFS-GPSDOs/info From: Brooke Clarke <brooke@pacific.net> To: Discussion of precise time and frequency measurement <time-nuts@febo.com> Sent: Thursday, August 11, 2016 1:36 PM Subject: Re: [time-nuts] Low cost SDR suitable for phase noise measurement? Hi Bob: The SDR-IQ has a lower frequency limit of 500 Hz. http://www.prc68.com/I/Bats.shtml#SDRIQ There is a mod that replaces the on board 66 MHz oscillator with one locked to 10 MHz. -- Have Fun, Brooke Clarke, N6GCE http://www.PRC68.com http://www.end2partygovernment.com/2012Issues.html The lesser of evils is still evil. -------- Original Message -------- > A number of posts have appeared about Zynq SDRs on the "Shera revisited" thread. So, I'd like to ask the more general question: Are there any low cost SDRs that are suitable for measuring phase noise when coupled with a DMTD? I believe what I'm looking for is something with enough bits to work in the audio range down to DC. Yes, I could use a modified sound card, but I'm really looking for something not sound card related. My thought was to use a DMTD with a heterodyne frequency of maybe 5KHz. > > Bob ----------------------------------------------------------------- > AE6RV.com > > GFS GPSDO list: > groups.yahoo.com/neo/groups/GFS-GPSDOs/info > _______________________________________________ > time-nuts mailing list -- time-nuts@febo.com > To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts > and follow the instructions there. > _______________________________________________ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.

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Re: [time-nuts] Shera revisted